32 lines
940 B
Markdown
32 lines
940 B
Markdown
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The humble beginnings of a UART loopback.
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``TOPMODULE=mkTop make v_compile`` to generate verilog. The generated verilog can
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be found in the ``verilog_RTL/`` folder.
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# Dependencies
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You'll need to install:
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1. [Yosys](https://github.com/YosysHQ/yosys) at git commit: 7ce5011c24b
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2. [nextpnr-0.4-36-gc8406b71](https://github.com/YosysHQ/nextpnr)
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3. [PrjTrellis](https://github.com/YosysHQ/prjtrellis) at git commit: 1.2.1-22-g35f5aff
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4. [openFPGALoader](https://github.com/trabucayre/openFPGALoader)
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# Programming the ULX3S
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Change into the folder containing this README, and then run ``
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```bash
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make -C ulx3s_fpga
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# You may need the following line to set your screen device config
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# to one parity and one stop bit. Tested working on MacOS, should
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# work on Linux.
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stty -f /dev/tty.usbserial-K00027 -cstopb -parenb
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screen /dev/tty.usbserial-K00027 9600
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```
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# Simulation
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TODO
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# Generating Verilog
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```bash
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TOPMODULE=mkTop make v_compile
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```
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