53 lines
1.4 KiB
Haskell
53 lines
1.4 KiB
Haskell
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package Deserializer(
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mkDeserialize,
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IDeserializer(..),
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State(..))
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where
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import ClkDivider
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import State
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interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
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get :: Bit 8
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putBitIn :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
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mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
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mkDeserialize fileHandle = do
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ftdiRxIn :: Wire(Bit 1) <- mkBypassWire
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shiftReg :: Reg(Bit 8) <- mkReg(0)
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ftdiState <- mkReg(IDLE)
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clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
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addRules $
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rules
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{-# ASSERT fire when enabled #-}
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"IDLE" : when (ftdiState == IDLE), (ftdiRxIn == 0) ==>
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do
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clkDivider.reset
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ftdiState := ftdiState' ftdiState
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{-# ASSERT fire when enabled #-}
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"NOT IDLE" : when (ftdiState /= IDLE), (clkDivider.isAdvancing) ==>
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do
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ftdiState := ftdiState' ftdiState
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{-# ASSERT fire when enabled #-}
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"SAMPLING" : when
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DATA(n) <- ftdiState,
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n >= 0,
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n <= 7,
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let sampleTrigger = clkDivider.isHalfCycle
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in sampleTrigger
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==>
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do
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shiftReg := ftdiRxIn ++ shiftReg[7:1]
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return $
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interface IDeserializer
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{get = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
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;putBitIn bit =
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ftdiRxIn := bit
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}
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