36 lines
759 B
Makefile
36 lines
759 B
Makefile
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BSV_PATH=$(shell dirname $(shell which bsc))/..
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BSV_LIBS=$(BSV_PATH)/lib/Verilog
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TOPMODULE=mkTop
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IDCODE ?= 0x41113043 # 85f
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all: prog
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../verilog_RTL/$(TOPMODULE).v: ../src/Top.bs
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V_SIM=verilator TOPMODULE=$(TOPMODULE) make -C ../ v_compile
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$(TOPMODULE).json: ../verilog_RTL/$(TOPMODULE).v
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yosys \
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-p "synth_ecp5 -top $(TOPMODULE) -json $@" \
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-E $(TOPMODULE).d \
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$< \
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$(BSV_LIBS)/Counter.v
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$(TOPMODULE).config: $(TOPMODULE).json
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nextpnr-ecp5 \
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--json $< \
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--textcfg $@ \
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--lpf ulx3s_v20.lpf \
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--85k \
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--package CABGA381
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$(TOPMODULE).bit: $(TOPMODULE).config
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ecppack --idcode $(IDCODE) $< $@
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.PHONY: prog
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prog: $(TOPMODULE).bit
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openFPGALoader -f -b ulx3s $<
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.PHONY: clean
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clean:
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rm -rf *.json *.config *.bit *.d
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make -C ../ clean
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