elucidate relationship between statement terminating EOL and advancing to keyword

TODO.md

@@ -1,30 +1,50 @@
  # General and Planning
  - [ ] might need many validation phases
-   - [ ] it's conceivable that one could construct a Yosys memory Cell with invalid parameters
+   - [ ] it's conceivable that one could construct a Yosys memory Cell 
+         with invalid parameters
    - [ ] detect mismatched sizes in assignments
- - [ ] need canonical form making it easy to run all these validation passes
+ - [ ] need canonical form making it easy to run all these validation 
- - [ ] are recursive slices inclusive
+       passes
- - [ ] what are the semantics of connection `<conn-stmt>`? Where is `<conn-stmt>` employed?
+ - [ ] are recursive slices inclusive?
+ - [ ] what are the semantics of connection `<conn-stmt>`? Where is 
+       `<conn-stmt>` employed?
  - [ ] Validate that `123456789[0:9][0:8]` is valid RTLIL
- - [ ] reload VSCode window
  - [ ] add validation section to README
  - [ ] just support Cell memV2
  - [ ] for value, what happens if we have 0 binary digits
- - [ ] ask ChatGPT about how to get my parser to ignore comments... - should probably wait until parser is finished before asking
+ - [ ] modify parser to ignore comments... - should probably wait until 
- - [ ] modify AST to support src tracking - needed to allow for human readable and correctable validation errors
+       parser is finished before asking
- - [ ] you could have a concated signal that gets sliced
+ - [ ] modify AST to support src tracking - needed to allow for human 
+       readable and correctable validation errors
  - [ ] when writing simulator, must specify directions on cell ports
- - [ ] in the <process>, why are we allowed to have <assign-stmt> before and after the optional <switch> stmt?
+ - [ ] in the <process>, why are we allowed to have <assign-stmt> before
- - [ ] make TODO file
+       and after the optional <switch> stmt?
  - [ ] inspect Chris's mini-RTLIL
- - [ ] split/organize imports/exports by section
  - [ ] add RST grammar file to repo
- - [ ] figure out whitespaces
+ - [ ] name parsers so that that we know where failures occured
- - [ ] I think only EOL terminated parsers should be responsible for pre-winding the Parsec scanner to the next non-space...
+ - [ ] may want to also derive equality statements
- - [ ] lift grammar into prover and show that all EOL terminated parsers are either followed by EOF or a keyword such "module", "autoidx", etc
+ - [x] replace both `pEol *> pMaybeWs` and `pEol <* pMaybeWs` 
- - [ ] name parsers that that we know where failures occured?
+       with `pEolAndAdvanceToNextNonWs`
+
+ # Parser Development
+  - [ ] Sync
+  - [ ] Process
+  - [ ] Module
+
+ # Parser Verification
+ - [ ] I think only EOL terminated parsers should be responsible 
+       for pre-winding the Parsec scanner to the next non-space...
+ - [ ] lift grammar into prover and show that all EOL terminated parsers
+       are either followed by EOF or a keyword such "module", "autoidx",
+       etc
  - [ ] first, manually inspect switch parser and try and see if it
-   can infinitely recurse... Then empirically validate against corpus
+       can infinitely recurse... Then empirically validate against
+       corpus
+
+# Simulation Behavior
+ - [ ] Figure out the computational semantics of what it means to
+       sync on `high`. I already understand the computational
+       semantics around synchronizing on `posedge` for example...
 
 # Simulation
  - [ ] dump to VCD

src/RTLILParser/AST.hs

@@ -35,7 +35,10 @@ module RTLILParser.AST (
 
     -- Switches
     Switch(..), SwitchStmt(..), Case(..), CaseStmt(..), Compare(..),
-    CaseBodyVariants(..), CaseBody(..)
+    CaseBodyVariants(..), CaseBody(..),
+
+    -- Syncs
+    Sync(..), SyncStmt(..), SyncType(..), UpdateStmt(..)
 ) where
 
 import Text.Read (Lexeme(Ident))
@@ -128,10 +131,11 @@ data CellBodyStmt   = CellBodyParameter
                     deriving (Show)
 
 -- Processes
-data DestSigSpec    = DestSigSpec SigSpec  deriving (Show)
+-- data ProcessBody    = ProcessBody [AssignStmt]
-data SrcSigSpec     = SrcSigSpec  SigSpec  deriving (Show)
 data AssignStmt     = AssignStmt  DestSigSpec SrcSigSpec
                       deriving (Show)
+data DestSigSpec    = DestSigSpec SigSpec  deriving (Show)
+data SrcSigSpec     = SrcSigSpec  SigSpec  deriving (Show)
 
 -- Switches
 data Switch         = Switch SwitchStmt [Case]
@@ -147,4 +151,18 @@ data CaseBodyVariants   = CaseBodySwitchVariant Switch
                         | CaseBodyAssignVariant AssignStmt
                         deriving (Show)
 data CaseBody       = CaseBody [CaseBodyVariants] deriving (Show)
+
 -- Syncs
+data Sync           = Sync SyncStmt [UpdateStmt] deriving (Show)
+data SyncStmt       = SigSpecPredicated SyncType SigSpec
+                    | Global
+                    | Init
+                    | Always
+                    deriving (Show)
+data SyncType       = Low
+                    | High
+                    | Posedge
+                    | Negedge
+                    | Edge
+                    deriving (Show)
+data UpdateStmt     = UpdateStmt DestSigSpec SrcSigSpec deriving (Show)

src/RTLILParser/Parser.hs

@@ -41,7 +41,10 @@ import RTLILParser.AST (
 
     -- Switches
     Switch(..), SwitchStmt(..), Case(..), CaseStmt(..), Compare(..),
-    CaseBodyVariants(..), CaseBody(..)
+    CaseBodyVariants(..), CaseBody(..),
+
+    -- Syncs
+    Sync(..), SyncStmt(..), SyncType(..), UpdateStmt(..)
     )
 import RTLILParser.Primitives(
     pWs
@@ -50,6 +53,7 @@ import RTLILParser.Primitives(
    ,pEol
    ,pOctal
    ,pEscapedChar
+   ,pEolAndAdvanceToNextNonWs
     )
 import Text.Parsec.Token (GenLanguageDef(caseSensitive))
 import GHC.IO.Handle.Types (Handle__(Handle__))
@@ -106,17 +110,20 @@ pString =
 
 -- Autoindex statements
 pAutoIdxStmt :: Parser AutoIdxStmt
-pAutoIdxStmt = AutoIdxStmt <$> (string "autoidx" *> pWs *> pInteger <* pEol <* pMaybeWs)
+pAutoIdxStmt = AutoIdxStmt 
+    <$> (string "autoidx" *> pWs *> 
+         pInteger <* pEolAndAdvanceToNextNonWs)
 
 -- Module
 pModuleStmt :: Parser Id
-pModuleStmt = string "module" *> pWs *> pId <* pEol <* pMaybeWs
+pModuleStmt = string "module" *> pWs *> pId <* 
+              pEolAndAdvanceToNextNonWs
 
 pParamStmt :: Parser ParamStmt
 pParamStmt = ParamStmt
     <$> (string "parameter" *> pWs *> pId <* pWs)
     <*> optionMaybe pConstant
-    <*  pEol <*  pMaybeWs
+    <*  pEolAndAdvanceToNextNonWs
 
 pConstant :: Parser Constant
 pConstant =
@@ -132,7 +139,7 @@ pAttrStmt :: Parser AttrStmt
 pAttrStmt = AttrStmt
     <$> (string "attribute" *> pWs *> pId)
     <*> (pWs *> pConstant)
-    <*  pEol <* pMaybeWs
+    <*  pEolAndAdvanceToNextNonWs
 
 -- Signal Specifications
 pSigSpec :: Parser SigSpec
@@ -169,7 +176,7 @@ pConnStmt :: Parser ConnStmt
 pConnStmt = ConnStmt
     <$> (string "connect" *> pWs *> pSigSpec)
     <*> (pWs *> pSigSpec)
-    <*  pEol <* pMaybeWs
+    <*  pEolAndAdvanceToNextNonWs
 
 -- Wires
 pWire :: Parser Wire
@@ -186,7 +193,7 @@ pWireStmt =
     <*> (WireId <$> pId)
     <*  pWs
     <*> many pWireOption
-    <*  pEol <* pMaybeWs
+    <*  pEolAndAdvanceToNextNonWs
 
 pWireId :: Parser WireId
 pWireId = WireId <$> pId
@@ -216,7 +223,7 @@ pMemoryStmt =
     <*> (MemoryID <$> pId)
     <*  pWs
     <*> many pMemoryOption
-    <*  pEol <* pMaybeWs
+    <*  pEolAndAdvanceToNextNonWs
 
 pMemoryOption :: Parser MemoryOption
 pMemoryOption =
@@ -239,7 +246,7 @@ pCellStmt = do
     cellType <- CellType <$> pId
     _ <- pWs
     cellId <- CellId <$> pId
-    _ <- pEol <* pMaybeWs
+    _ <- pEolAndAdvanceToNextNonWs
     return $ CellStmt cellId cellType
 
 pCellBodyStmt :: Parser CellBodyStmt
@@ -255,37 +262,33 @@ pCellBodyParameter = do
     _       <- string "parameter" <* pWs
     sign    <- optionMaybe pParameterSign <* pMaybeWs
     id      <- pId
-    const   <- pConstant <* pEol <* pMaybeWs
+    const   <- pConstant <* pEolAndAdvanceToNextNonWs
     return $ CellBodyParameter sign id const
 
 pCellBodyConnect :: Parser CellBodyStmt
 pCellBodyConnect = do
     _       <- string "connect" <* pWs
     id      <- pId <* pWs
-    sigSpec <- pSigSpec <* pEol <* pMaybeWs
+    sigSpec <- pSigSpec <* pEolAndAdvanceToNextNonWs
     return  $ CellConnect id sigSpec
 
 -- Processes
+-- pProcessBody :: 
+pAssignStmt :: Parser AssignStmt
+pAssignStmt = AssignStmt
+    <$> (string "assign" *> pWs *> pDestSigSpec)
+    <*> (pWs *> pSrcSigSpec <* pEolAndAdvanceToNextNonWs)
+
 pDestSigSpec :: Parser DestSigSpec
 pDestSigSpec = DestSigSpec <$> pSigSpec
 
 pSrcSigSpec :: Parser SrcSigSpec
 pSrcSigSpec = SrcSigSpec <$> pSigSpec
 
-pAssignStmt :: Parser AssignStmt
+pProcEndStmt :: Parser ()
-pAssignStmt = AssignStmt
+pProcEndStmt = void (string "end" <* pEolAndAdvanceToNextNonWs)
-    <$> (string "assign" *> pWs *> pDestSigSpec)
-    <*> (pWs *> pSrcSigSpec <* pEol <* pMaybeWs)
 
 -- Switches
--- - [ ] <switch>            ::= <switch-stmt> <case>* <switch-end-stmt>
--- - [ ] <switch-stmt>       ::= <attr-stmt>* switch <sigspec> <eol>
--- - [ ] <case>              ::= <attr-stmt>* <case-stmt> <case-body>
--- - [x] <case-stmt>         ::= case <compare>? <eol>
--- - [x] <compare>           ::= <sigspec> (, <sigspec>)*
--- - [ ] <case-body>         ::= (<switch> | <assign-stmt>)*
--- - [ ] <switch-end-stmt>   ::= end <eol>
-
 pSwitch :: Parser Switch
 pSwitch = Switch
     <$> pSwitchStmt
@@ -295,7 +298,7 @@ pSwitchStmt :: Parser SwitchStmt
 pSwitchStmt = do
     attrs   <- many pAttrStmt
     _       <- string "switch"  <* pWs
-    sigspec <- pSigSpec <* pEol <* pMaybeWs
+    sigspec <- pSigSpec <* pEolAndAdvanceToNextNonWs
     return $ SwitchStmt sigspec attrs
 
 pCase :: Parser Case
@@ -309,7 +312,7 @@ pCaseStmt = CaseStmt
     <$> (
         string "case" *> pWs 
         *> optionMaybe pCompare 
-        <* pEol <* pMaybeWs)
+        <* pEolAndAdvanceToNextNonWs)
 
 pCompare :: Parser Compare
 pCompare = Compare
@@ -324,11 +327,21 @@ pCaseBodyVariant =
         (CaseBodyAssignVariant <$> pAssignStmt)
 
 pSwitchEndStmt :: Parser ()
-pSwitchEndStmt = void (string "end" *> pEol *> pMaybeWs)
+pSwitchEndStmt = void (string "end" *> pEolAndAdvanceToNextNonWs)
 
 -- Syncs
+pSyncType :: Parser SyncType
+pSyncType =
+    (Low        <$ string "low"     )   <|>
+    (High       <$ string "high"    )   <|>
+    (Posedge    <$ string "posedge" )   <|>
+    (Negedge    <$ string "negedge" )   <|>
+    (Edge       <$ string "edge"    )
 
-
+pUpdateStmt :: Parser UpdateStmt
+pUpdateStmt = UpdateStmt
+    <$> (string "update" *> pWs *> pDestSigSpec)
+    <*> (pWs *> pSrcSigSpec <* pEolAndAdvanceToNextNonWs)
 
  
 -- would correspond to `123456789[0:9][0:8]`

src/RTLILParser/Primitives.hs

@@ -5,6 +5,7 @@ module RTLILParser.Primitives(
    ,pEol
    ,pOctal
    ,pEscapedChar
+   ,pEolAndAdvanceToNextNonWs
 ) where
 
 import Control.Monad (void)
@@ -43,3 +44,6 @@ pNonWs = noneOf " \t\r\n"
 
 pEol :: Parser String
 pEol = many1 (oneOf "\r\n")
+
+pEolAndAdvanceToNextNonWs :: Parser ()
+pEolAndAdvanceToNextNonWs = void $ pEol *> pMaybeWs