improve README
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README.md
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README.md
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@ -30,12 +30,26 @@ input, and just have fun!
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# Status
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# Status
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Right now Haskellator can successfully parse some valid RTLIL into [an AST](./src/RTLIL/Syntax.hs).
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Right now Haskellator can successfully parse RTLIL emitted from
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We are currently working on expanding the RTLIL that can be parsed to include
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Amaranth lang as well as RTLIL emitted from running Yosys
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[RTLIL](https://github.com/YosysHQ/yosys/blob/main/kernel/rtlil.h)
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over large VexRISCV designs.
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emitted from Amaranth Lang.
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Currently targetting RTLIL in Yosys .47.
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You can generate an RTLIL corpus to test Haskellator against right
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from this repo by doing the following:
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```bash
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git clone --recursive git@github.com:JoyOfHardware/Haskellator.git
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pushd rtlil-corpus; nix-shell; exit; popd
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```
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Now run a command like the following to parse some rtlil into Haskell
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data structures found in `src/RTLILParser/AST.hs`.
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```bash
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nix-shell
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rtlil-parse rtlil-corpus/corpus/gpio.il gpio.hs
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Output written to gpio.hs
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```
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# Usage
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# Usage
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@ -59,9 +73,12 @@ $ rtlil-parse rtlil_file.il parsed_ast.hs
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# Limitations
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# Limitations
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- Does not support propagating non-two state logic, that is, no
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- Does not support propagating non-two state logic, that is, no
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support for X or Z values. Default behavior is to reject such
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support for X or Z values. Default behavior is to successfully
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input although future iterations may support initializing X and
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parser such input. In the future, we will have validation phases
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Z to 0.
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that reject circuits with X or Z values.
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We may eventually support initializing X and Z values to 0.
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- All cycles in circuit graphs must have at one D Flip-Flop on the
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- All cycles in circuit graphs must have at one D Flip-Flop on the
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cycle path. This requirement necesarily pre-cludes simulation of
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cycle path. This requirement necesarily pre-cludes simulation of
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circuits such as NAND level-resolution SRAMs. The main reason for
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circuits such as NAND level-resolution SRAMs. The main reason for
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@ -73,7 +90,10 @@ $ rtlil-parse rtlil_file.il parsed_ast.hs
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as asynchronous FIFOs, but I plan to make sure simulation of such
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as asynchronous FIFOs, but I plan to make sure simulation of such
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circuits is possible and correct.
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circuits is possible and correct.
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# Lessons Learned
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# Sponsors
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- Should have written parser to be token based where after consuming
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and capturing token, we consume and discard all following whitespaces
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<p align="center">
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as well as comments...
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<a href="https://NLnet.nl">
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<img src="assets/nlnet_logo.png" width="269" alt="Logo NLnet">
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</a>
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</p>
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