diff --git a/README.md b/README.md
index 1b2b8dc..33ba7b5 100644
--- a/README.md
+++ b/README.md
@@ -35,6 +35,8 @@ We are currently working on expanding the RTLIL that can be parsed to include
 [RTLIL](https://github.com/YosysHQ/yosys/blob/main/kernel/rtlil.h) 
 emitted from Amaranth Lang.
 
+Currently targetting RTLIL in Yosys .47.
+
 # Usage
 
 ## Run and Build With Nix(Linux and MacOS)
@@ -50,6 +52,9 @@ $ rtlil-parse test/corpus/xprop_dffe_1nnd_wrapped_xprop.il -o parsed1.ast
 # TODO
  - [ ] automated CICD on gitea on personal servers
  - [ ] update to have support for four state logic by converting 'X' and 'Z' to zero
+ - [ ] validation pass that checks that `ConstantInteger Int` is
+   32 bits, that is, within range  \[-2147483648, 2147483648)
+ - [ ] Reverse/repair cell-stmt
 
 # Limitations
  - Does not support propagating non-two state logic, that is, no
diff --git a/atoms.txt b/atoms.txt
index b8574ba..90a8c27 100644
--- a/atoms.txt
+++ b/atoms.txt
@@ -1,6 +1,6 @@
  - [x] <id> ::= <public-id> | <autogen-id>
- - [x] <public-id> ::= “" <nonws>+
- - [x] <autogen-id> ::= “” <nonws>+
+ - [x] <public-id> ::= "\" <nonws>+
+ - [x] <autogen-id> ::= "$" <nonws>+
  - [x] <value> ::= <decimal-digit>+ ’ <binary-digit>*
  - [x] <decimal-digit> ::= “0” | “1” | “2” | “3” | “4” | “5” | “6” | “7” | “8” | “9”
  - [x] <binary-digit> ::= “0” | “1” | “x” | “z” | “m” | “-“
@@ -9,24 +9,24 @@
  - [x] <autoidx-stmt> ::= “autoidx” <integer> <eol>
  - [ ] <module> ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
  - [x] <module-stmt> ::= “module” <id> <eol>
- - [ ] <module-body> ::= (<param-stmt> <wire> <memory> <cell> <process> )*
- - [ ] <param-stmt> ::= “parameter” <id> <constant>? <eol>
- - [ ] <constant> ::= <value> | <integer> | <string>
+ - [ ] <module-body> ::= (<param-stmt> | <wire> | <memory> | <cell> | <process> )*
+ - [x] <param-stmt> ::= “parameter” <id> <constant>? <eol>
+ - [x] <constant> ::= <value> | <integer> | <string>
  - [x] <module-end-stmt> ::= “end” <eol>
- - [ ] <attr-stmt> ::= “attribute” <id> <constant> <eol>
- - [ ] <sigspec> ::= <constant> <sigspec> “[” <integer> (“:” <integer>)? “]” “{” <sigspec>* “}”
+ - [x] <attr-stmt> ::= “attribute” <id> <constant> <eol>
+ - [ ] <sigspec> ::= <constant> | <wire-id> | <sigspec> “[” <integer> (“:” <integer>)? “]” | “{” <sigspec>* “}”
  - [ ] <conn-stmt> ::= “connect” <sigspec> <sigspec> <eol>
  - [ ] <wire> ::= <attr-stmt>* <wire-stmt>
  - [ ] <wire-stmt> ::= “wire” <wire-option>* <wire-id> <eol>
  - [ ] <wire-id> ::= <id>
- - [ ] <wire-option> ::= “width” <integer> “offset” <integer> “input” <integer> “output” <integer> “inout” <integer> “upto” “signed”
+ - [ ] <wire-option> ::= “width” <integer> | “offset” <integer> | “input” <integer> | “output” <integer> | “inout” <integer> | “upto” | “signed”
  - [ ] <memory> ::= <attr-stmt>* <memory-stmt>
  - [ ] <memory-stmt> ::= “memory” <memory-option>* <id> <eol>
- - [ ] <memory-option> ::= “width” <integer> “size” <integer> “offset” <integer>
+ - [ ] <memory-option> ::= “width” <integer> | “size” <integer> | “offset” <integer>
  - [ ] <cell> ::= <attr-stmt>* <cell-stmt> <cell-body-stmt>* <cell-end-stmt>
- - [ ] <cell-stmt> ::= “cell” <cell-id> <cell-type> <eol>
- - [ ] <cell-id> ::= <id>
- - [ ] <cell-type> ::= <id>
+ - [ ] <cell-stmt> ::= "cell" <cell-id> <cell-type> <eol>
+ - [x] <cell-id> ::= <id>
+ - [x] <cell-type> ::= <id>
  - [ ] <cell-body-stmt> ::= “parameter” (“signed” | “real”)? <id> <constant> <eol> “connect” <id> <sigspec> <eol>
  - [ ] <cell-end-stmt> ::= “end” <eol>
  - [ ] <process> ::= <attr-stmt>* <proc-stmt> <process-body> <proc-end-stmt>
diff --git a/src/RTLILParser/AST.hs b/src/RTLILParser/AST.hs
index 3244f81..e62784a 100644
--- a/src/RTLILParser/AST.hs
+++ b/src/RTLILParser/AST.hs
@@ -1,18 +1,31 @@
 module RTLILParser.AST(
-    PublicId(..),
-    AutogenId(..),
-    AutoIdxStmt(..),
-    Id(..),
-    Value(..)
+    AutoIdxStmt(..),    ParamStmt(..), AutogenId(..),
+    Constant(..),       CellStmt(..),  PublicId(..),
+    AttrStmt(..),       Value(..),     Id(..),
+    CellId(..),         CellType(..), WireId(..),
+    SigSpec(..)
     ) where
 import Text.Read (Lexeme(Ident))
+import Data.Functor.Contravariant (Contravariant)
+import GHC.RTS.Flags (DoCostCentres(CostCentresAll))
 
 data PublicId       = PublicId      String  deriving (Show)
 data AutogenId      = AutogenId     String  deriving (Show)
 data Id             = Public    PublicId
                     | Autogen   AutogenId
                     deriving (Show)
+data WireId         = WireId    Id
+                    deriving (Show)
 data AutoIdxStmt    = AutoIdxStmt   Int     deriving (Show)
+data AttrStmt       = AttrStmt  Id Constant deriving (Show)
+data CellStmt       = CellStmt  CellId CellType  deriving (Show)
+data CellId         = CellId    Id deriving (Show)
+data CellType       = CellType  Id deriving (Show)
+data SigSpec        = SigSpecConstant   Constant
+                    | SigSpecWireId     WireId
+                    | SigSpecSlice      SigSpec Int (Maybe Int)
+                    | SigSpecConcat     [SigSpec]
+                    deriving (Show)
 data Value = Value
     { width :: Int
     , value :: Int
@@ -22,3 +35,8 @@ data Constant = ConstantValue   Value
               | ConstantInteger Int
               | ConstantString  String
               deriving (Show)
+data ParamStmt = ParamStmt
+    { paramId       :: Id
+    , paramConstant :: Maybe Constant
+    }
+    deriving (Show)
diff --git a/src/RTLILParser/Parser.hs b/src/RTLILParser/Parser.hs
index d13c199..bb46c11 100644
--- a/src/RTLILParser/Parser.hs
+++ b/src/RTLILParser/Parser.hs
@@ -7,13 +7,13 @@ import Control.Monad (void)
 import Text.Parsec
 import Text.Parsec.String (Parser)
 import RTLILParser.AST(
-    PublicId(..), 
-    Id(..),
-    AutogenId(..),
-    AutoIdxStmt(..),
-    Value(..)
+    AutoIdxStmt(..),    ParamStmt(..), AutogenId(..),
+    Constant(..),       CellStmt(..),  PublicId(..),
+    AttrStmt(..),       Value(..),     Id(..),
+    CellId(..),         CellType(..), WireId(..),
+    SigSpec(..)
     )
-import Util(binaryStringToInt) 
+import Util(binaryStringToInt)
 import RTLILParser.Primitives(pEscapedChar)
 
 -- https://github.com/YosysHQ/yosys/blob/111b747d2797238eadf541879848492a9d34909a/frontends/rtlil/rtlil_lexer.l#L88C1-L88C17
@@ -36,6 +36,9 @@ pId :: Parser Id
 pId = Public  <$> pPublicId
   <|> Autogen <$> pAutogenId
 
+pWireId :: Parser WireId
+pWireId = WireId <$> pId
+
 decimalDigit :: Parser Char
 decimalDigit = oneOf "0123456789"
 
@@ -45,7 +48,7 @@ pBinaryDigit :: Parser Char
 pBinaryDigit = oneOf "01"
 
 pString :: Parser String
-pString = 
+pString =
     between delimiter delimiter parseString
     where
         delimiter = char '"'
@@ -53,7 +56,7 @@ pString =
 
 
 pValue :: Parser Value
-pValue = Value  <$> pInteger 
+pValue = Value  <$> pInteger
                 <*> (binaryStringToInt <$> many1 pBinaryDigit)
 
 pInteger :: Parser Int
@@ -65,6 +68,11 @@ pInteger = do
         Just _  -> -value
         Nothing ->  value
 
+pConstant :: Parser Constant
+pConstant =
+    try (ConstantValue <$> pValue)
+    <|> (ConstantInteger <$> pInteger)
+    <|> (ConstantString <$> pString)
 
 pAutoIdxStmt :: Parser AutoIdxStmt
 pAutoIdxStmt = AutoIdxStmt <$> (string "autoidx" *> pWs *> pInteger <* pEol)
@@ -75,6 +83,29 @@ pModuleStmt = string "module" *> pWs *> pId <* pEol
 pModuleEndStmt :: Parser ()
 pModuleEndStmt = void (string "end")
 
+pParamStmt :: Parser ParamStmt
+pParamStmt = ParamStmt
+    <$> (string "parameter" *> pWs *> pId)
+    <*> optionMaybe (pWs *> pConstant)
+    <*  pEol
+
+pAttrStmt :: Parser AttrStmt
+pAttrStmt = AttrStmt
+    <$> (string "attribute" *> pWs *> pId)
+    <*> (pWs *> pConstant)
+    <*  pEol
+
+pCellStmt :: Parser CellStmt
+pCellStmt = do
+    _ <- string "cell"
+    _ <- pWs
+    cellId <- CellId <$> pId
+    _ <- pWs
+    cellType <- CellType <$> pId
+    _ <- pEol
+    return $ CellStmt cellId cellType
+
+
 -- pModuleStmt :: Parser ()
 -- pModuleStmt =