diff --git a/src/RTLILParser/AST.hs b/src/RTLILParser/AST.hs index 7d556d0..f67731a 100644 --- a/src/RTLILParser/AST.hs +++ b/src/RTLILParser/AST.hs @@ -1,12 +1,13 @@ module RTLILParser.AST( - AutoIdxStmt(..) ,ParamStmt(..) ,AutogenId(..) - ,Constant(..) ,CellStmt(..) ,PublicId(..) - ,AttrStmt(..) ,Value(..) ,Id(..) - ,CellId(..) ,CellType(..) ,WireId(..) - ,SigSpec(..) ,Slice(..) ,ConnStmt(..) - ,WireOption(..) ,WireStmt(..) ,Wire(..) - ,MemoryOption(..) ,MemoryStmt(..) ,Memory(..) - ,MemoryID(..) + AutoIdxStmt(..) ,ParamStmt(..) ,AutogenId(..) + ,Constant(..) ,CellStmt(..) ,PublicId(..) + ,AttrStmt(..) ,Value(..) ,Id(..) + ,CellId(..) ,CellType(..) ,WireId(..) + ,SigSpec(..) ,Slice(..) ,ConnStmt(..) + ,WireOption(..) ,WireStmt(..) ,Wire(..) + ,MemoryOption(..) ,MemoryStmt(..) ,Memory(..) + ,MemoryID(..) ,CellBodyStmt(..) ,ParameterSign(..) + ,Cell(..) ) where import Text.Read (Lexeme(Ident)) import Data.Functor.Contravariant (Contravariant) @@ -84,9 +85,18 @@ data MemoryOption = MemoryOptionWidth Int deriving (Show) -- Cells +data Cell = Cell CellStmt [AttrStmt] [CellBodyStmt] + deriving (Show) data CellStmt = CellStmt CellId CellType deriving (Show) data CellId = CellId Id deriving (Show) data CellType = CellType Id deriving (Show) +data ParameterSign = Signed | Real deriving (Show) +data CellBodyStmt = CellBodyParameter + (Maybe ParameterSign) + Id + Constant + | CellConnect Id SigSpec + deriving (Show) -- Processes -- Switches diff --git a/src/RTLILParser/Parser.hs b/src/RTLILParser/Parser.hs index add95ca..b86abc3 100644 --- a/src/RTLILParser/Parser.hs +++ b/src/RTLILParser/Parser.hs @@ -4,14 +4,15 @@ import Control.Monad (void) import Text.Parsec import Text.Parsec.String (Parser) import RTLILParser.AST( - AutoIdxStmt(..) ,ParamStmt(..) ,AutogenId(..) - ,Constant(..) ,CellStmt(..) ,PublicId(..) - ,AttrStmt(..) ,Value(..) ,Id(..) - ,CellId(..) ,CellType(..) ,WireId(..) - ,SigSpec(..) ,Slice(..) ,ConnStmt(..) - ,WireOption(..) ,WireStmt(..) ,Wire(..) - ,MemoryOption(..) ,MemoryStmt(..) ,Memory(..) - ,MemoryID(..) + AutoIdxStmt(..) ,ParamStmt(..) ,AutogenId(..) + ,Constant(..) ,CellStmt(..) ,PublicId(..) + ,AttrStmt(..) ,Value(..) ,Id(..) + ,CellId(..) ,CellType(..) ,WireId(..) + ,SigSpec(..) ,Slice(..) ,ConnStmt(..) + ,WireOption(..) ,WireStmt(..) ,Wire(..) + ,MemoryOption(..) ,MemoryStmt(..) ,Memory(..) + ,MemoryID(..) ,CellBodyStmt(..) ,ParameterSign(..) + ,Cell(..) ) import Util(binaryStringToInt) import RTLILParser.Primitives( @@ -83,8 +84,8 @@ pModuleStmt = string "module" *> pWs *> pId <* pEol pParamStmt :: Parser ParamStmt pParamStmt = ParamStmt - <$> (string "parameter" *> pWs *> pId) - <*> optionMaybe (pWs *> pConstant) + <$> (string "parameter" *> pWs *> pId <* pWs) + <*> optionMaybe pConstant <* pEol pConstant :: Parser Constant @@ -194,16 +195,46 @@ pMemoryOption = try (MemoryOptionOffset <$> (string "offset" *> pWs *> pInteger)) -- Cells +pCell :: Parser Cell +pCell = do + attrStmts <- many pAttrStmt + cellStmt <- pCellStmt + cellBodyStmts <- many pCellBodyStmt + return $ Cell cellStmt attrStmts cellBodyStmts + pCellStmt :: Parser CellStmt pCellStmt = do _ <- string "cell" _ <- pWs - cellId <- CellId <$> pId - _ <- pWs cellType <- CellType <$> pId + _ <- pWs + cellId <- CellId <$> pId _ <- pEol return $ CellStmt cellId cellType +pCellBodyStmt :: Parser CellBodyStmt +pCellBodyStmt = pCellBodyParameter <|> pCellBodyConnect + +pParameterSign :: Parser ParameterSign +pParameterSign = + (Signed <$ string "signed") <|> + (Real <$ string "real") + +pCellBodyParameter :: Parser CellBodyStmt +pCellBodyParameter = do + _ <- string "parameter" <* pWs + sign <- optionMaybe pParameterSign <* pMaybeWs + id <- pId + const <- pConstant <* pEol + return $ CellBodyParameter sign id const + +pCellBodyConnect :: Parser CellBodyStmt +pCellBodyConnect = do + _ <- string "connect" <* pWs + id <- pId <* pWs + sigSpec <- pSigSpec <* pEol + return $ CellConnect id sigSpec + -- Processes -- Switches -- Syncs