From 43ae657a5bbde4454086d76acdc1f6608f2f2c57 Mon Sep 17 00:00:00 2001
From: Yehowshua Immanuel <yehowshua@yehowshuaimmanuel.com>
Date: Mon, 9 Dec 2024 00:03:46 -0500
Subject: [PATCH] presumable finished implementing types for process...

---
 TODO.md                | 13 ++++++++-----
 src/RTLILParser/AST.hs | 15 +++++++++++++--
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/TODO.md b/TODO.md
index cfded04..cf19f54 100644
--- a/TODO.md
+++ b/TODO.md
@@ -18,20 +18,23 @@
        readable and correctable validation errors
  - [ ] when writing simulator, must specify directions on cell ports
  - [ ] in the <process>, why are we allowed to have <assign-stmt> before
-       and after the optional <switch> stmt?
+       and after the optional <switch> stmt? If the ordering here is
+       semantically significant, then modify AST to only have single
+       `[AssignStmt]` field and update parser behavior accordingly.
  - [ ] inspect Chris's mini-RTLIL
  - [ ] add RST grammar file to repo
  - [ ] name parsers so that that we know where failures occured
  - [ ] may want to also derive equality statements
  - [x] replace both `pEol *> pMaybeWs` and `pEol <* pMaybeWs` 
        with `pEolAndAdvanceToNextNonWs`
- - [ ] Check inline sequencing of whitespace parsers in do blocks.
+ - [x] Check inline sequencing of whitespace parsers in do blocks.
        Terminating instances of `pWs` should be preceeded by `<*`
 
  # Parser Development
-  - [x] Sync
-  - [ ] Process
-  - [ ] Module
+ - [x] Sync
+ - [ ] Process
+ - [ ] Rewrite `pWireStmt` and `pMemoryStmt` using do-notation...
+ - [ ] Module
 
  # Parser Verification
  - [ ] I think only EOL terminated parsers should be responsible 
diff --git a/src/RTLILParser/AST.hs b/src/RTLILParser/AST.hs
index 2e4d10b..5207597 100644
--- a/src/RTLILParser/AST.hs
+++ b/src/RTLILParser/AST.hs
@@ -31,7 +31,8 @@ module RTLILParser.AST (
     CellBodyStmt(..),
 
     -- Processes
-    DestSigSpec(..), SrcSigSpec(..), AssignStmt(..),
+    Process(..), ProcStmt(..), ProcessBody(..), AssignStmt(..),
+    DestSigSpec(..), SrcSigSpec(..),
 
     -- Switches
     Switch(..), SwitchStmt(..), Case(..), CaseStmt(..), Compare(..),
@@ -39,6 +40,8 @@ module RTLILParser.AST (
 
     -- Syncs
     Sync(..), SyncStmt(..), SyncType(..), UpdateStmt(..)
+
+
 ) where
 
 import Text.Read (Lexeme(Ident))
@@ -131,7 +134,15 @@ data CellBodyStmt   = CellBodyParameter
                     deriving (Show)
 
 -- Processes
--- data ProcessBody    = ProcessBody [AssignStmt]
+data Process        = Process ProcStmt [AttrStmt] ProcessBody
+                      deriving (Show)
+data ProcStmt       = ProcStmt Id deriving (Show)
+data ProcessBody    = ProcessBody 
+                        [AssignStmt]
+                        Switch 
+                        [AssignStmt] 
+                        [Sync] 
+                    deriving (Show)
 data AssignStmt     = AssignStmt  DestSigSpec SrcSigSpec
                       deriving (Show)
 data DestSigSpec    = DestSigSpec SigSpec  deriving (Show)