2024-12-09 18:20:21 +00:00
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# General and Planning
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2024-12-09 01:37:10 +00:00
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- [ ] might need many validation phases
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2024-12-09 04:00:00 +00:00
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- [ ] it's conceivable that one could construct a Yosys memory Cell
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with invalid parameters
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2024-12-09 01:37:10 +00:00
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- [ ] detect mismatched sizes in assignments
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2024-12-09 04:00:00 +00:00
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- [ ] need canonical form making it easy to run all these validation
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passes
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- [ ] are recursive slices inclusive?
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2024-12-11 00:22:21 +00:00
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- [ ] you can apparently have empty SigConCats - but what does this
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even mean?
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2024-12-10 19:41:45 +00:00
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- [ ] what are the semantics of connection `<conn-stmt>`?
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2024-12-09 01:37:10 +00:00
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- [ ] Validate that `123456789[0:9][0:8]` is valid RTLIL
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- [ ] add validation section to README
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- [ ] just support Cell memV2
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- [ ] for value, what happens if we have 0 binary digits
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2024-12-09 04:00:00 +00:00
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- [ ] modify AST to support src tracking - needed to allow for human
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readable and correctable validation errors
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2024-12-09 01:37:10 +00:00
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- [ ] when writing simulator, must specify directions on cell ports
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2024-12-10 18:35:31 +00:00
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- [ ] track RTLIL EBNF spec vs RTLIL Lex/Yacc implementation
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[deviation issue][deviation-issue]
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- [ ] Update issue above with fact that `<memwr>` is also missing
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2024-12-09 04:00:00 +00:00
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- [ ] may want to also derive equality statements
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2024-12-09 05:03:46 +00:00
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- [x] Check inline sequencing of whitespace parsers in do blocks.
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2024-12-09 04:42:03 +00:00
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Terminating instances of `pWs` should be preceeded by `<*`
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2024-12-09 04:00:00 +00:00
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2024-12-09 18:20:21 +00:00
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# Parser Development
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2024-12-09 07:34:11 +00:00
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- [ ] Remove weird GHC imports
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2024-12-10 18:35:31 +00:00
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- [ ] Test `fsm1.il` which has recursive slices on line 180
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2024-12-09 18:20:21 +00:00
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- [ ] Embed locs in AST
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2024-12-10 18:35:31 +00:00
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- [ ] Name new parsers
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- [ ] Remove `a` and `val` from exports
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2024-12-10 22:04:47 +00:00
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- [ ] Permit all binary characters. Add validation pass later.
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- [ ] Correct comment parser
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- [ ] What does it mean to have an empty sigspec concat in
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`{ <sigspec>* }`
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2024-12-09 04:00:00 +00:00
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2024-12-09 18:20:21 +00:00
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# Parser Verification
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2024-12-09 04:00:00 +00:00
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- [ ] I think only EOL terminated parsers should be responsible
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2024-12-10 18:35:31 +00:00
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for advancing the Parsec scanner to the next token
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2024-12-09 04:00:00 +00:00
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- [ ] lift grammar into prover and show that all EOL terminated parsers
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are either followed by EOF or a keyword such "module", "autoidx",
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etc
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# Simulation Behavior
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- [ ] Figure out the computational semantics of what it means to
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sync on `high`. I already understand the computational
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semantics around synchronizing on `posedge` for example...
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2024-12-09 01:37:10 +00:00
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2024-12-09 04:00:00 +00:00
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# Simulation
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2024-12-09 01:37:10 +00:00
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- [ ] dump to VCD
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- [ ] Write dynamically typed executor in Haskell
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- [ ] Subsequent IR passes may emerge natrually
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# Optimizations
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2024-12-10 18:35:31 +00:00
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- [ ] squeeze out recursive slices
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[deviation-issue]: https://github.com/YosysHQ/yosys/issues/4811
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