$date
	Sat Feb  6 19:39:57 2016
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module simple_tb $end
$scope module s $end
$var wire 4 ! A [3:0] $end
$var wire 4 " B [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b11 "
b1010 !
$end
#50
b101 "
b1100 !
#150
b0 "
b0 !
#250