From 4336994571b7f051ccf28fe8481b400381e41a3e Mon Sep 17 00:00:00 2001
From: Artturin <Artturin@artturin.com>
Date: Tue, 1 Oct 2024 22:46:35 +0300
Subject: [PATCH] Add test

---
 flake.nix               |  14 ++++++++++++++
 tests/test-upstream.out | Bin 0 -> 4892 bytes
 tests/test.c            |  31 +++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100755 tests/test-upstream.out
 create mode 100644 tests/test.c

diff --git a/flake.nix b/flake.nix
index 9fe1350..3f46fc4 100644
--- a/flake.nix
+++ b/flake.nix
@@ -49,6 +49,20 @@
           default = self.packages.${system}.smi;
         };
 
+        checks = {
+          simple =
+            pkgs.runCommand "test"
+              {
+                # Goes up to 7
+                NIX_DEBUG = 0;
+              }
+              ''
+                mkdir -p $out
+                ${self.packages.${system}.tt-gcc}/bin/riscv32-unknown-elf-gcc ${./tests/test.c} -o $out/test
+                ${self.packages.${system}.tt-gcc}/bin/riscv32-unknown-elf-gcc -mblackhole ${./tests/test.c} -o $out/test-wormhole
+              '';
+        };
+
         formatter = pkgs.nixfmt-rfc-style;
       }
     );
diff --git a/tests/test-upstream.out b/tests/test-upstream.out
new file mode 100755
index 0000000000000000000000000000000000000000..76359cc2e1dc03a4ca18051012d0780ba8a834a8
GIT binary patch
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HcmV?d00001

diff --git a/tests/test.c b/tests/test.c
new file mode 100644
index 0000000..a5ac9d2
--- /dev/null
+++ b/tests/test.c
@@ -0,0 +1,31 @@
+#define GPIO_BASE (0x48000000U) // Base address for GPIO port (e.g., GPIOA on STM32)
+#define RCC_BASE  (0x40021000U) // Base address for RCC (Reset and Clock Control)
+
+#define RCC_AHB2ENR (*(volatile unsigned int *)(RCC_BASE + 0x4C))
+#define GPIOA_MODER (*(volatile unsigned int *)(GPIO_BASE + 0x00))
+#define GPIOA_ODR   (*(volatile unsigned int *)(GPIO_BASE + 0x14))
+
+#define LED_PIN 5 // Assume the LED is connected to GPIO pin 5
+
+void delay(volatile unsigned int count) {
+    while (count--);
+}
+
+int main(void) {
+    // Enable the clock for GPIOA
+    RCC_AHB2ENR |= (1 << 0); // Enable GPIOA clock
+
+    // Set GPIOA pin 5 to output mode (01)
+    GPIOA_MODER &= ~(3 << (LED_PIN * 2)); // Clear mode bits for pin 5
+    GPIOA_MODER |=  (1 << (LED_PIN * 2)); // Set mode to 01 (output)
+
+    while (1) {
+        // Toggle the LED
+        GPIOA_ODR ^= (1 << LED_PIN);
+
+        // Delay
+        delay(100000);
+    }
+
+    return 0;
+}