Artturin
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  • Joined on 2025-01-03
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Artturin created pull request ReferenceProjects/riscv-bluespec-classic#18 2025-04-19 10:55:55 +00:00
flake: Add missing input
Artturin created branch fix-compat in Artturin/riscv-bluespec-classic 2025-04-19 10:55:44 +00:00
Artturin pushed to fix-compat at Artturin/riscv-bluespec-classic 2025-04-19 10:55:44 +00:00
9d897fccdc flake: Add missing input
44324eb803 need to start re-thinking structure of uart etc
d03cceb283 Merge pull request 'Add flake' (#7) from Artturin/riscv-bluespec-classic:addflake into main
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Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-18 16:01:53 +00:00
7bc43946a9 Add compat files for non flakes users
Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-18 16:00:22 +00:00
b89090f3ce flake.lock: Update
Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-18 15:57:57 +00:00
14d20e3101 flake: Fix bluespec bsc binary
71c938c912 flake.lock: Update
c02e7b0de6 flake: Install the same file that fpga-starter-project-uart installed
7471c0188a Make make fpga work
1622e3ab6b Remove all trailing spaces
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Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-04 14:23:28 +00:00
23b5de5cd3 flake: Fix bluespec bsc binary
d8ca756e43 flake.lock: Update
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Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-03 19:28:05 +00:00
8b6ca3accc flake: Install the same file that fpga-starter-project-uart installed
Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-02 00:15:22 +00:00
7836ac5f3f Make make fpga work
d48621521a Remove all trailing spaces
41c1e910dd Add initial flake
7c32974f7b update readme
76e542ff36 tested and seems to be working
Compare 15 commits »
Artturin created pull request ReferenceProjects/riscv-bluespec-classic#7 2025-04-02 00:11:21 +00:00
WIP: Add flake
Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-02 00:10:42 +00:00
2308058d33 Make make fpga work
Artturin pushed to addflake at Artturin/riscv-bluespec-classic 2025-04-02 00:05:07 +00:00
3afca5b0f9 Remove all trailing spaces
1c8ebeb238 Add initial flake
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Artturin created branch addflake in Artturin/riscv-bluespec-classic 2025-04-02 00:05:07 +00:00
Artturin created repository Artturin/riscv-bluespec-classic 2025-04-01 23:56:18 +00:00
Artturin commented on issue ReferenceProjects/riscv-bluespec-classic#1 2025-03-19 18:05:08 +00:00
Add Proper Nix Flake

How long does TOPMODULE=mkSim make b_compile b_link b_sim Bluesim simulation phase take for you?

Artturin pushed to addnix at Artturin/RiscV-Formal 2025-03-13 23:44:49 +00:00
8037eeba19 flake.nix: Remove cross glibc
Artturin pushed to addnix at Artturin/RiscV-Formal 2025-03-13 23:40:16 +00:00
1dd246294e flake.nix: Correct glibc location
Artturin pushed to addnix at Artturin/RiscV-Formal 2025-03-13 23:17:30 +00:00
0960ceb53a rv_tests/hello_world: Rename PREFIX var to CROSS_PREFIX and make it configurable
ac8a2ea238 flake.nix: Comments
56a80fe749 Riscv config
2b9895f1cc Use newer ghc
c75ad4fa70 Remove stack.yaml
Compare 37 commits »
Artturin created pull request Yehowshua/RiscV-Formal#4 2025-02-22 20:38:15 +00:00
Add flake
Artturin pushed to addnix at Artturin/RiscV-Formal 2025-02-22 20:37:59 +00:00
fa03829139 Use newer ghc
783ec90a45 Remove stack.yaml
67fcd15f42 After make clean and make, this file changes
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