56 lines
1.7 KiB
Plaintext
56 lines
1.7 KiB
Plaintext
// bsc -sim -u -g mkTestbench Testbench.bsv; bsc -sim -e mkTestbench -o simBRAM; ./simBRAM -V
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import BRAM::*;
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import StmtFSM::*;
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import Clocks::*;
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function BRAMRequest#(Bit#(8), Bit#(8)) makeRequest(Bool write, Bit#(8) addr, Bit#(8) data);
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return BRAMRequest{
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write: write,
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responseOnWrite:False,
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address: addr,
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datain: data
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};
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endfunction
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(* synthesize *)
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module mkTestbench();
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Reg#(UInt#(3)) count <- mkReg(0);
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BRAM_Configure cfg = defaultValue;
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cfg.allowWriteResponseBypass = False;
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// BRAM2Port#(Bit#(8), Bit#(8)) dut0 <- mkBRAM2Server(cfg);
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cfg.loadFormat = tagged Hex "bram2.txt";
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BRAM1Port#(Bit#(8), Bit#(8)) dut1 <- mkBRAM1Server(cfg);
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rule counting;
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count <= count + 1;
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endrule
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//Define StmtFSM to run tests
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Stmt test =
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(seq
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delay(10);
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action
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$display("count = %d", count);
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dut1.portA.request.put(makeRequest(False, 0, 0));
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endaction
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action
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$display("count = %d", count);
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$display("dut1read[0] = %x", dut1.portA.response.get);
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dut1.portA.request.put(makeRequest(False, 1, 0));
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endaction
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action
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$display("count = %d", count);
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$display("dut1read[1] = %x", dut1.portA.response.get);
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dut1.portA.request.put(makeRequest(False, 2, 0));
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endaction
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action
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$display("count = %d", count);
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$display("dut1read[2] = %x", dut1.portA.response.get);
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endaction
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delay(100);
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action
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$finish();
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endaction
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endseq);
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mkAutoFSM(test);
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endmodule |