53 lines
1.4 KiB
Plaintext
53 lines
1.4 KiB
Plaintext
package Serializer;
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import ClkDivider::*;
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import State::*;
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export mkSerialize;
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export ISerializer(..);
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export State(..);
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function Bit#(1) serialize(State state, Bit#(8) dataReg);
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case (state) matches
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tagged START : return 1'b0;
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tagged DATA .n : return dataReg[n];
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default : return 1'b1;
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endcase
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endfunction
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interface ISerializer#(numeric type clkFreq, numeric type baudRate);
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(* always_enabled , always_ready *)
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method Action putBit8(Bit#(8) bit8Val);
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(* always_ready *)
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method Bit#(1) bitLineOut();
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endinterface
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module mkSerialize#(Handle fileHandle)(ISerializer#(clkFreq, baudRate));
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Wire#(Bit#(1)) ftdiTxOut <- mkDWire(1);
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Reg#(Bit#(8)) dataReg <- mkReg(0);
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Reg#(State) ftdiState <- mkReg(IDLE);
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ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
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(* fire_when_enabled *)
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rule advanceUartState (ftdiState != IDLE && clkDivider.isAdvancing());
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ftdiState <= ftdiStateNext(ftdiState);
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endrule
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(* fire_when_enabled *)
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rule bitLine (ftdiState != IDLE);
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ftdiTxOut <= serialize(ftdiState, dataReg);
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endrule
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method Action putBit8(Bit#(8) bit8Val) if (ftdiState == IDLE);
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clkDivider.reset();
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dataReg <= bit8Val;
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ftdiState <= ftdiStateNext(ftdiState);
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endmethod
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method Bit#(1) bitLineOut;
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return ftdiTxOut;
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endmethod
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endmodule
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endpackage |