56 lines
1.4 KiB
Haskell
56 lines
1.4 KiB
Haskell
-- TOPMODULE=mkTop make b_compile
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package Top(mkTop, ITop(..), mkSim) where
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import Deserializer
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import Serializer
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type FCLK = 25_000_000
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type BAUD = 9_600
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interface ITop =
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ftdi_rxd :: Bit 1 {-# always_ready #-}
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led :: Bit 8 {-# always_ready #-}
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ftdi_txd :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
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{-# properties mkTop={verilog} #-}
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mkTop :: Module (ITop)
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mkTop = do
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fileHandle <- openFile "compile.log" WriteMode
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deserializer :: (IDeserializer FCLK BAUD) <- mkDeserialize fileHandle
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serializer :: (ISerializer FCLK BAUD) <- mkSerialize fileHandle
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ftdiBitIn :: Wire(Bit 1) <- mkBypassWire
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rxReg :: Reg(Bit 8) <- mkReg(0)
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messageM $ "Hallo!!" + (realToString 5)
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addRules $
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rules
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when True ==>
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do
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rxReg := deserializer.get
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serializer.putBit8 $ deserializer.get
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when True ==>
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deserializer.putBitIn ftdiBitIn
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return $
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interface ITop
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{ftdi_rxd = serializer.bitLineOut
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;led = rxReg
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;ftdi_txd bitIn = ftdiBitIn := bitIn}
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mkSim :: Module Empty
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mkSim = do
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-- count :: Reg(UInt 3) <- mkReg(0)
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count :: Reg(UInt 3) <- mkReg(0)
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addRules $
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rules
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"count" : when True ==> action
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count := unpack ((1'b1) ++ (pack count)[2:1])
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$display count
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"end sim" : when (count == 6) ==> action
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$finish
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return $
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interface Empty |