need to start re-thinking structure of uart etc

Reviewed-on: ReferenceProjects/riscv-bluespec-classic#7

Makefile

@@ -60,7 +60,7 @@ $(BDPI_OBJ): $(BDPI_SRC)
 
 BSC_LINK_FLAGS += -keep-fires
 
-BSC_PATHS = -p bs/Bus/:bs/:bs/Tests/:bsv/:+
+BSC_PATHS = -p bs/Uart/:bs/Bus/:bs/:bs/Tests/:bsv/:+
 
 .PHONY: help
 help:
@@ -159,7 +159,7 @@ v_sim_vcd:
 # ----------------------------------------------------------------
 
 fpga:
-	make -C ulx3s_fpga mkTop.bit
+	make -C ulx3s_fpga mkTop.bit prog
 
 .PHONY: clean
 clean:

bs/Uart/Serializer.bs

@@ -15,8 +15,8 @@ serialize ftdiState dataReg =
         _        -> 1'b1
 
 interface (ISerializer :: # -> # -> *) clkFreq baudRate =
-  putBit8    :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
-  bitLineOut ::  Bit 1            {-# always_ready #-}
+  putBit8    :: (Bit 8) -> Action
+  bitLineOut ::  Bit 1
 
 mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
 mkSerialize fileHandle = do