Merge pull request 'Add flake' (#7) from Artturin/riscv-bluespec-classic:addflake into main
Reviewed-on: ReferenceProjects/riscv-bluespec-classic#7
This commit is contained in:
commit
d03cceb283
2
.gitignore
vendored
2
.gitignore
vendored
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@ -16,6 +16,8 @@ verilog_RTL
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# files generated for FPGA ULX3s implementation
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ulx3s_fpga/mkTop.d
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ulx3s_fpga/mkTop.json
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ulx3s_fpga/mkTop.bit
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ulx3s_fpga/mkTop.config
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# generated experiment outputs
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experiments/bram/*.cxx
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2
Makefile
2
Makefile
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@ -159,7 +159,7 @@ v_sim_vcd:
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# ----------------------------------------------------------------
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fpga:
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make -C ulx3s_fpga
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make -C ulx3s_fpga mkTop.bit
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.PHONY: clean
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clean:
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@ -49,4 +49,3 @@ mkSerialize fileHandle = do
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ftdiState := ftdiState' ftdiState
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when (ftdiState == IDLE)
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bitLineOut = ftdiTxOut
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25
default.nix
Normal file
25
default.nix
Normal file
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@ -0,0 +1,25 @@
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{
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system ? builtins.currentSystem,
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}:
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let
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lock = builtins.fromJSON (builtins.readFile ./flake.lock);
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root = lock.nodes.${lock.root};
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inherit (lock.nodes.${root.inputs.flake-compat}.locked)
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owner
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repo
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rev
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narHash
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;
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flake-compat = fetchTarball {
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url = "https://github.com/${owner}/${repo}/archive/${rev}.tar.gz";
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sha256 = narHash;
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};
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flake = import flake-compat {
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inherit system;
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src = ./.;
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};
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in
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flake.defaultNix
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61
flake.lock
Normal file
61
flake.lock
Normal file
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@ -0,0 +1,61 @@
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{
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"nodes": {
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"nixpkgs": {
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"locked": {
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"lastModified": 1744536153,
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"narHash": "sha256-awS2zRgF4uTwrOKwwiJcByDzDOdo3Q1rPZbiHQg/N38=",
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"owner": "NixOS",
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"repo": "nixpkgs",
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"rev": "18dd725c29603f582cf1900e0d25f9f1063dbf11",
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"type": "github"
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},
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"original": {
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"owner": "NixOS",
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"ref": "nixpkgs-unstable",
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"repo": "nixpkgs",
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"type": "github"
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}
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},
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"root": {
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"inputs": {
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"nixpkgs": "nixpkgs",
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"utils": "utils"
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}
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},
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"systems": {
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"locked": {
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"lastModified": 1681028828,
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"narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
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"owner": "nix-systems",
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"repo": "default",
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"rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
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"type": "github"
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},
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"original": {
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"owner": "nix-systems",
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"repo": "default",
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"type": "github"
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}
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},
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"utils": {
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"inputs": {
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"systems": "systems"
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},
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"locked": {
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"lastModified": 1731533236,
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"narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=",
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"owner": "numtide",
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"repo": "flake-utils",
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"rev": "11707dc2f618dd54ca8739b309ec4fc024de578b",
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"type": "github"
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},
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"original": {
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"owner": "numtide",
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"repo": "flake-utils",
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"type": "github"
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}
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}
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},
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"root": "root",
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"version": 7
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}
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78
flake.nix
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78
flake.nix
Normal file
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@ -0,0 +1,78 @@
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{
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inputs = {
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nixpkgs = {
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url = "github:NixOS/nixpkgs/nixpkgs-unstable";
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};
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utils.url = "github:numtide/flake-utils";
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};
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outputs =
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inputs:
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inputs.utils.lib.eachDefaultSystem (
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system:
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let
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pkgs = import inputs.nixpkgs {
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localSystem = system;
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overlays = [
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(final: prev: {
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riscv-bluespec-classic = pkgs.callPackage (
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{
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stdenv,
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bluespec,
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nextpnr,
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openfpgaloader,
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trellis,
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which,
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yosys,
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}:
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stdenv.mkDerivation {
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pname = "riscv-bluespec-classic";
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version = "0.1.0";
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src = ./.;
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# Versions can be checked with
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# `nix eval --json ".#riscv-bluespec-classic.nativeBuildInputs" | nix-shell -p jq --run jq`
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nativeBuildInputs = [
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bluespec
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nextpnr
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openfpgaloader
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trellis
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which
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yosys
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];
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makeFlags = [
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"fpga"
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];
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installPhase = ''
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runHook preInstall
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mkdir -p "$out"
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cp "./ulx3s_fpga/mkTop.bit" "$out/"
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runHook postInstall
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'';
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}
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) { };
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})
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];
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};
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in
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{
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packages = {
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default = inputs.self.packages."${system}".riscv-bluespec-classic;
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riscv-bluespec-classic = pkgs.riscv-bluespec-classic;
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};
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devShells.default =
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with pkgs;
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mkShell {
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inputsFrom = [ riscv-bluespec-classic ];
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};
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}
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);
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}
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35
shell.nix
35
shell.nix
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@ -1,14 +1,25 @@
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{ pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/d34a98666913267786d9ab4aa803a1fc75f81f4d.tar.gz") {} }:
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{
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system ? builtins.currentSystem,
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}:
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let
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lock = builtins.fromJSON (builtins.readFile ./flake.lock);
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pkgs.mkShell {
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buildInputs = [
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pkgs.yosys
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pkgs.nextpnr
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pkgs.bluespec
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pkgs.yosys-bluespec
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];
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root = lock.nodes.${lock.root};
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inherit (lock.nodes.${root.inputs.flake-compat}.locked)
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owner
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repo
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rev
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narHash
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;
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shellHook = ''
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echo "Dev environment for Manna Chip."
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'';
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}
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flake-compat = fetchTarball {
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url = "https://github.com/${owner}/${repo}/archive/${rev}.tar.gz";
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sha256 = narHash;
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};
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flake = import flake-compat {
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inherit system;
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src = ./.;
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};
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in
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flake.shellNix
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@ -5,7 +5,7 @@ IDCODE ?= 0x41113043 # 85f
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all: prog
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../verilog_RTL/$(TOPMODULE).v: ../src/Top.bsv
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../verilog_RTL/$(TOPMODULE).v: ../bs/Top.bs
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V_SIM=verilator TOPMODULE=$(TOPMODULE) make -C ../ v_compile
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$(TOPMODULE).json: ../verilog_RTL/$(TOPMODULE).v
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@ -21,6 +21,7 @@ $(TOPMODULE).config: $(TOPMODULE).json
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--textcfg $@ \
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--lpf ulx3s_v20.lpf \
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--85k \
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--lpf-allow-unconstrained \
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--package CABGA381
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$(TOPMODULE).bit: $(TOPMODULE).config
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