Artturin/riscv-bluespec-classic
1
0
Fork 0
forked from ReferenceProjects/riscv-bluespec-classic
Code Pull requests Activity

update README with instructions for simulating main core

Browse source
This commit is contained in:
Yehowshua Immanuel 2024-03-20 02:48:49 -04:00
parent 338cdac474
commit 95631e77b8
1 changed files with 9 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
README.md
View file

@ -37,7 +37,15 @@ screen /dev/tty.usbserial-K00027 9600
# Simulation # Simulation
## Main Chip Core ## Main Chip Core
TODO The following command will simulate the UART loopback
by having the bluespec sources call some C code that
commandeers the tty, disables echo, exposes the tty write
buffer to bluespec(what the user types), and exposes
a buffer bluespec can use to write to terminal.
```bash
TOPMODULE=mkSim make b_all
```
## Experiments ## Experiments
See experiments README. See experiments README.