quieter builds, more type uniformity, full compiles

- made builds less verbose on Mac by removing `-cpp`
 - made type constructors for most instances of `(UInt (TLog n))`
 - addressed cases where types built upon `(UInt (TLog n))` may have
   a max value of `n`, which necessitates changing the type to
   ` (UInt (TLog (TAdd 1 n)))`
 - compiler wouldn't fully evaluate types unless mkBus was
   instantiated
This commit is contained in:
Yehowshua Immanuel 2025-04-10 20:46:53 -04:00
parent 548a2f26bd
commit 5efef8b19c
7 changed files with 58 additions and 20 deletions

View file

@ -51,7 +51,6 @@ BSC_COMP_FLAGS += \
-aggressive-conditions \
-no-warn-action-shadowing \
-check-assert \
-cpp \
-show-schedule \
+RTS -K128M -RTS -show-range-conflict \
$(BSC_COMP_FLAG1) $(BSC_COMP_FLAG2) $(BSC_COMP_FLAG3)

View file

@ -1,4 +1,4 @@
package Bus(mkBus) where
package Bus(mkBus, Bus(..)) where
import Types
import BusTypes
@ -18,6 +18,12 @@ busRequestToAddr req = case req of
BusReadRequest (ReadRequest addr _) -> addr
BusWriteRequest (WriteRequest addr _) -> addr
dummyRule :: Rules
dummyRule =
rules
"test rule": when True ==> do
$display "test rule"
mkBus :: (Addr -> Maybe ServerIdx)
-> Module (Bus inFlightTransactions numClients numServers)
mkBus busMap = do
@ -25,24 +31,41 @@ mkBus busMap = do
tagEngineByClientVec :: Vector numClients (TagEngine inFlightTransactions)
tagEngineByClientVec <- replicateM mkTagEngine
-- Arbitration for clients to send requests to servers
clientArbiter :: Arbiter.Arbiter_IFC numClients
clientArbiter <- mkArbiter False
clientArbiters :: Arbiter.Arbiter_IFC numClients
clientArbiters <- mkArbiter False
serverArbiters :: Arbiter.Arbiter_IFC numServers
serverArbiters <- mkArbiter False
dummyVar :: Reg(Bool)
dummyVar <- mkReg False
-- Queues to hold requests from clients to arbiter
-- Queues to hold requests from clients
clientRequestQueues :: Vector numClients (FIFOF (TaggedBusRequest inFlightTransactions))
clientRequestQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
-- Queues to hold responses from arbiter to clients
-- Queues to hold responses to clients
clientResponseQueues :: Vector numClients (FIFOF (TaggedBusResponse inFlightTransactions))
clientResponseQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
-- -- Queues to hold requests from arbiter to server
-- serverRequestQueues :: Vector numServers (FIFOF (TaggedBusRequest inFlightTransactions))
-- serverRequestQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
let clientRouter :: Vector numClients (Rules)
clientRouter = genWith $ \clientIdx ->
rules
"test rule": when True ==> do
$display "client test rule"
let clientRouter :: Rules
clientRouter =
rules
"test rule": when True ==> do
$display "client test rule"
-- Rules
addRules |>
rules
"test rule": when True ==> do
$display "test rule"
<+> clientRouter
-- Client interface vector
let clients :: Vector numClients (BusClient inFlightTransactions)

View file

@ -13,7 +13,7 @@ import Types
import Vector
import TagEngine
type MkClientTagType a = (UInt (TLog a))
type MkClientTagType numClients = (UInt (TLog numClients))
type ServerIdx = Integer
data BusError

View file

@ -1,4 +1,8 @@
package ClkDivider(mkClkDivider, ClkDivider(..)) where
package ClkDivider(
mkClkDivider,
MkClkDivType,
ClkDivider(..)
) where
interface (ClkDivider :: # -> *) hi =
{
@ -7,11 +11,13 @@ interface (ClkDivider :: # -> *) hi =
;isHalfCycle :: Bool
}
type MkClkDivType maxCycles = (UInt (TLog (TAdd 1 maxCycles)))
mkClkDivider :: Handle -> Module (ClkDivider hi)
mkClkDivider fileHandle = do
counter <- mkReg(0 :: UInt (TLog hi))
let hi_value :: UInt (TLog hi) = (fromInteger $ valueOf hi)
let half_hi_value :: UInt (TLog hi) = (fromInteger $ valueOf (TDiv hi 2))
counter <- mkReg(0 :: MkClkDivType hi)
let hi_value :: (MkClkDivType hi) = (fromInteger $ valueOf hi)
let half_hi_value :: (MkClkDivType hi) = (fromInteger $ valueOf (TDiv hi 2))
let val :: Real = (fromInteger $ valueOf hi)
let msg = "Clock Div Period : " + (realToString val) + "\n"

View file

@ -11,13 +11,13 @@ interface (Core :: # -> *) clkFreq = {
mkCore :: Module (Core clkFreq)
mkCore = do
counter :: Reg (UInt (TLog clkFreq)) <- mkReg 0
counter :: Reg (MkClkDivType clkFreq) <- mkReg 0
tickSecond :: Wire Bool <- mkDWire False
uartOut :: Wire (Bit 8) <- mkWire;
ledOut :: Reg (Bit 8) <- mkReg 0
let clkFreqInt :: Integer = valueOf clkFreq
let clkFreqUInt :: UInt (TLog clkFreq) = fromInteger clkFreqInt
let clkFreqUInt :: (MkClkDivType clkFreq) = fromInteger clkFreqInt
let val :: Real = fromInteger clkFreqInt
messageM $ "mkCore clkFreq" + realToString val

View file

@ -9,7 +9,7 @@ import Util
import FIFO
import SpecialFIFOs
type MkTagType numTags = (UInt (TLog numTags))
type MkTagType numTags = (UInt (TLog (TAdd 1 numTags)))
interface (TagEngine :: # -> *) numTags =
requestTag :: ActionValue (MkTagType numTags)

View file

@ -10,6 +10,9 @@ import TagEngine
import List
import ActionSeq
import Vector
import BusTypes
import TagEngineTester
type FCLK = 25000000
@ -57,11 +60,18 @@ mkTop = do
mkSim :: Module Empty
mkSim = do
_ :: Empty <- mkTagEngineTester
initCFunctions :: Reg Bool <- mkReg False;
core :: Core FCLK <- mkCore;
initCFunctions :: Reg Bool <- mkReg False
core :: Core FCLK <- mkCore
let busMap _ = Just 0
bus :: (Bus 4 2 2) <- mkBus busMap
addRules $
rules
"test bus": when True ==>
do
let server = (Vector.select bus.servers 0)
result <- server.consumeRequest
$display (fshow result)
"initCFunctionsOnce": when not initCFunctions ==>
do
initTerminal