quieter builds, more type uniformity, full compiles
- made builds less verbose on Mac by removing `-cpp` - made type constructors for most instances of `(UInt (TLog n))` - addressed cases where types built upon `(UInt (TLog n))` may have a max value of `n`, which necessitates changing the type to ` (UInt (TLog (TAdd 1 n)))` - compiler wouldn't fully evaluate types unless mkBus was instantiated
This commit is contained in:
parent
548a2f26bd
commit
5efef8b19c
1
Makefile
1
Makefile
|
@ -51,7 +51,6 @@ BSC_COMP_FLAGS += \
|
||||||
-aggressive-conditions \
|
-aggressive-conditions \
|
||||||
-no-warn-action-shadowing \
|
-no-warn-action-shadowing \
|
||||||
-check-assert \
|
-check-assert \
|
||||||
-cpp \
|
|
||||||
-show-schedule \
|
-show-schedule \
|
||||||
+RTS -K128M -RTS -show-range-conflict \
|
+RTS -K128M -RTS -show-range-conflict \
|
||||||
$(BSC_COMP_FLAG1) $(BSC_COMP_FLAG2) $(BSC_COMP_FLAG3)
|
$(BSC_COMP_FLAG1) $(BSC_COMP_FLAG2) $(BSC_COMP_FLAG3)
|
||||||
|
|
41
bs/Bus.bs
41
bs/Bus.bs
|
@ -1,4 +1,4 @@
|
||||||
package Bus(mkBus) where
|
package Bus(mkBus, Bus(..)) where
|
||||||
|
|
||||||
import Types
|
import Types
|
||||||
import BusTypes
|
import BusTypes
|
||||||
|
@ -18,6 +18,12 @@ busRequestToAddr req = case req of
|
||||||
BusReadRequest (ReadRequest addr _) -> addr
|
BusReadRequest (ReadRequest addr _) -> addr
|
||||||
BusWriteRequest (WriteRequest addr _) -> addr
|
BusWriteRequest (WriteRequest addr _) -> addr
|
||||||
|
|
||||||
|
dummyRule :: Rules
|
||||||
|
dummyRule =
|
||||||
|
rules
|
||||||
|
"test rule": when True ==> do
|
||||||
|
$display "test rule"
|
||||||
|
|
||||||
mkBus :: (Addr -> Maybe ServerIdx)
|
mkBus :: (Addr -> Maybe ServerIdx)
|
||||||
-> Module (Bus inFlightTransactions numClients numServers)
|
-> Module (Bus inFlightTransactions numClients numServers)
|
||||||
mkBus busMap = do
|
mkBus busMap = do
|
||||||
|
@ -25,24 +31,41 @@ mkBus busMap = do
|
||||||
tagEngineByClientVec :: Vector numClients (TagEngine inFlightTransactions)
|
tagEngineByClientVec :: Vector numClients (TagEngine inFlightTransactions)
|
||||||
tagEngineByClientVec <- replicateM mkTagEngine
|
tagEngineByClientVec <- replicateM mkTagEngine
|
||||||
|
|
||||||
-- Arbitration for clients to send requests to servers
|
clientArbiters :: Arbiter.Arbiter_IFC numClients
|
||||||
clientArbiter :: Arbiter.Arbiter_IFC numClients
|
clientArbiters <- mkArbiter False
|
||||||
clientArbiter <- mkArbiter False
|
|
||||||
|
serverArbiters :: Arbiter.Arbiter_IFC numServers
|
||||||
|
serverArbiters <- mkArbiter False
|
||||||
|
|
||||||
dummyVar :: Reg(Bool)
|
dummyVar :: Reg(Bool)
|
||||||
dummyVar <- mkReg False
|
dummyVar <- mkReg False
|
||||||
|
|
||||||
-- Queues to hold requests from clients to arbiter
|
-- Queues to hold requests from clients
|
||||||
clientRequestQueues :: Vector numClients (FIFOF (TaggedBusRequest inFlightTransactions))
|
clientRequestQueues :: Vector numClients (FIFOF (TaggedBusRequest inFlightTransactions))
|
||||||
clientRequestQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
|
clientRequestQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
|
||||||
|
|
||||||
-- Queues to hold responses from arbiter to clients
|
-- Queues to hold responses to clients
|
||||||
clientResponseQueues :: Vector numClients (FIFOF (TaggedBusResponse inFlightTransactions))
|
clientResponseQueues :: Vector numClients (FIFOF (TaggedBusResponse inFlightTransactions))
|
||||||
clientResponseQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
|
clientResponseQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
|
||||||
|
|
||||||
-- -- Queues to hold requests from arbiter to server
|
let clientRouter :: Vector numClients (Rules)
|
||||||
-- serverRequestQueues :: Vector numServers (FIFOF (TaggedBusRequest inFlightTransactions))
|
clientRouter = genWith $ \clientIdx ->
|
||||||
-- serverRequestQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
|
rules
|
||||||
|
"test rule": when True ==> do
|
||||||
|
$display "client test rule"
|
||||||
|
|
||||||
|
let clientRouter :: Rules
|
||||||
|
clientRouter =
|
||||||
|
rules
|
||||||
|
"test rule": when True ==> do
|
||||||
|
$display "client test rule"
|
||||||
|
|
||||||
|
-- Rules
|
||||||
|
addRules |>
|
||||||
|
rules
|
||||||
|
"test rule": when True ==> do
|
||||||
|
$display "test rule"
|
||||||
|
<+> clientRouter
|
||||||
|
|
||||||
-- Client interface vector
|
-- Client interface vector
|
||||||
let clients :: Vector numClients (BusClient inFlightTransactions)
|
let clients :: Vector numClients (BusClient inFlightTransactions)
|
||||||
|
|
|
@ -13,7 +13,7 @@ import Types
|
||||||
import Vector
|
import Vector
|
||||||
import TagEngine
|
import TagEngine
|
||||||
|
|
||||||
type MkClientTagType a = (UInt (TLog a))
|
type MkClientTagType numClients = (UInt (TLog numClients))
|
||||||
type ServerIdx = Integer
|
type ServerIdx = Integer
|
||||||
|
|
||||||
data BusError
|
data BusError
|
||||||
|
|
|
@ -1,4 +1,8 @@
|
||||||
package ClkDivider(mkClkDivider, ClkDivider(..)) where
|
package ClkDivider(
|
||||||
|
mkClkDivider,
|
||||||
|
MkClkDivType,
|
||||||
|
ClkDivider(..)
|
||||||
|
) where
|
||||||
|
|
||||||
interface (ClkDivider :: # -> *) hi =
|
interface (ClkDivider :: # -> *) hi =
|
||||||
{
|
{
|
||||||
|
@ -7,11 +11,13 @@ interface (ClkDivider :: # -> *) hi =
|
||||||
;isHalfCycle :: Bool
|
;isHalfCycle :: Bool
|
||||||
}
|
}
|
||||||
|
|
||||||
|
type MkClkDivType maxCycles = (UInt (TLog (TAdd 1 maxCycles)))
|
||||||
|
|
||||||
mkClkDivider :: Handle -> Module (ClkDivider hi)
|
mkClkDivider :: Handle -> Module (ClkDivider hi)
|
||||||
mkClkDivider fileHandle = do
|
mkClkDivider fileHandle = do
|
||||||
counter <- mkReg(0 :: UInt (TLog hi))
|
counter <- mkReg(0 :: MkClkDivType hi)
|
||||||
let hi_value :: UInt (TLog hi) = (fromInteger $ valueOf hi)
|
let hi_value :: (MkClkDivType hi) = (fromInteger $ valueOf hi)
|
||||||
let half_hi_value :: UInt (TLog hi) = (fromInteger $ valueOf (TDiv hi 2))
|
let half_hi_value :: (MkClkDivType hi) = (fromInteger $ valueOf (TDiv hi 2))
|
||||||
|
|
||||||
let val :: Real = (fromInteger $ valueOf hi)
|
let val :: Real = (fromInteger $ valueOf hi)
|
||||||
let msg = "Clock Div Period : " + (realToString val) + "\n"
|
let msg = "Clock Div Period : " + (realToString val) + "\n"
|
||||||
|
|
|
@ -11,13 +11,13 @@ interface (Core :: # -> *) clkFreq = {
|
||||||
|
|
||||||
mkCore :: Module (Core clkFreq)
|
mkCore :: Module (Core clkFreq)
|
||||||
mkCore = do
|
mkCore = do
|
||||||
counter :: Reg (UInt (TLog clkFreq)) <- mkReg 0
|
counter :: Reg (MkClkDivType clkFreq) <- mkReg 0
|
||||||
tickSecond :: Wire Bool <- mkDWire False
|
tickSecond :: Wire Bool <- mkDWire False
|
||||||
uartOut :: Wire (Bit 8) <- mkWire;
|
uartOut :: Wire (Bit 8) <- mkWire;
|
||||||
ledOut :: Reg (Bit 8) <- mkReg 0
|
ledOut :: Reg (Bit 8) <- mkReg 0
|
||||||
|
|
||||||
let clkFreqInt :: Integer = valueOf clkFreq
|
let clkFreqInt :: Integer = valueOf clkFreq
|
||||||
let clkFreqUInt :: UInt (TLog clkFreq) = fromInteger clkFreqInt
|
let clkFreqUInt :: (MkClkDivType clkFreq) = fromInteger clkFreqInt
|
||||||
let val :: Real = fromInteger clkFreqInt
|
let val :: Real = fromInteger clkFreqInt
|
||||||
|
|
||||||
messageM $ "mkCore clkFreq" + realToString val
|
messageM $ "mkCore clkFreq" + realToString val
|
||||||
|
|
|
@ -9,7 +9,7 @@ import Util
|
||||||
import FIFO
|
import FIFO
|
||||||
import SpecialFIFOs
|
import SpecialFIFOs
|
||||||
|
|
||||||
type MkTagType numTags = (UInt (TLog numTags))
|
type MkTagType numTags = (UInt (TLog (TAdd 1 numTags)))
|
||||||
|
|
||||||
interface (TagEngine :: # -> *) numTags =
|
interface (TagEngine :: # -> *) numTags =
|
||||||
requestTag :: ActionValue (MkTagType numTags)
|
requestTag :: ActionValue (MkTagType numTags)
|
||||||
|
|
14
bs/Top.bs
14
bs/Top.bs
|
@ -10,6 +10,9 @@ import TagEngine
|
||||||
import List
|
import List
|
||||||
import ActionSeq
|
import ActionSeq
|
||||||
|
|
||||||
|
import Vector
|
||||||
|
import BusTypes
|
||||||
|
|
||||||
import TagEngineTester
|
import TagEngineTester
|
||||||
|
|
||||||
type FCLK = 25000000
|
type FCLK = 25000000
|
||||||
|
@ -57,11 +60,18 @@ mkTop = do
|
||||||
mkSim :: Module Empty
|
mkSim :: Module Empty
|
||||||
mkSim = do
|
mkSim = do
|
||||||
_ :: Empty <- mkTagEngineTester
|
_ :: Empty <- mkTagEngineTester
|
||||||
initCFunctions :: Reg Bool <- mkReg False;
|
initCFunctions :: Reg Bool <- mkReg False
|
||||||
core :: Core FCLK <- mkCore;
|
core :: Core FCLK <- mkCore
|
||||||
|
let busMap _ = Just 0
|
||||||
|
bus :: (Bus 4 2 2) <- mkBus busMap
|
||||||
|
|
||||||
addRules $
|
addRules $
|
||||||
rules
|
rules
|
||||||
|
"test bus": when True ==>
|
||||||
|
do
|
||||||
|
let server = (Vector.select bus.servers 0)
|
||||||
|
result <- server.consumeRequest
|
||||||
|
$display (fshow result)
|
||||||
"initCFunctionsOnce": when not initCFunctions ==>
|
"initCFunctionsOnce": when not initCFunctions ==>
|
||||||
do
|
do
|
||||||
initTerminal
|
initTerminal
|
||||||
|
|
Loading…
Reference in a new issue