Remove all trailing spaces

`git grep -I --name-only -z -e '' | xargs -0 sed -i 's/[ \t]\+\(\r\?\)$/\1/'`

Remember to setup your editor so that these are automatically removed :)

Makefile

@@ -99,7 +99,7 @@ b_all: b_compile  b_link    b_sim
 b_compile:
 	mkdir  -p build_b_sim
 	@echo Compiling for Bluesim ...
-	bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE) 
+	bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE)
 	@echo Compiling for Bluesim finished
 
 .PHONY: b_link
@@ -141,7 +141,7 @@ v_compile:
 .PHONY: v_link
 v_link: $(BDPI_OBJ)
 	@echo Linking for Verilog sim ...
-	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v 
+	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v
 	@echo Linking for Verilog sim finished
 
 .PHONY: v_sim

bs/Bus/Bus.bs

@@ -30,8 +30,8 @@ mkBus serverMap = do
     tagEngineByClientVec :: Vector numClients (TagEngine inFlightTransactions)
     tagEngineByClientVec <- replicateM mkTagEngine
 
-    -- There are `numClients` clients, each of which needs its own client 
+    -- There are `numClients` clients, each of which needs its own client
-    -- response arbiter as there are `numServer` servers that may wish to 
+    -- response arbiter as there are `numServer` servers that may wish to
     -- submit a response to a given client. Furthermore the rule that routes
     -- client requests to servers makes for another potential submitter to
     -- the client response arbiter as it may determine that a request is
@@ -56,7 +56,7 @@ mkBus serverMap = do
     clientResponseQueues :: Vector numClients (FIFOF (TaggedBusResponse inFlightTransactions))
     clientResponseQueues <- replicateM (mkSizedBypassFIFOF (valueOf inFlightTransactions))
 
-    -- The following two vectors of single depth FIFOs make it easier to push/pull data 
+    -- The following two vectors of single depth FIFOs make it easier to push/pull data
     -- to/from internal server methods as they provide back-pressure in both directions,
     -- and behave as a wire when queue is empty.
     -- If looking at the example bus.drawio diagram, the following two vectors effectively
@@ -89,7 +89,7 @@ mkBus serverMap = do
                 selectedClientRespArbiter = select responseArbiterByClient clientIdx
 
                 clientRouterRule :: Rules
-                clientRouterRule =  clientRouteRequest 
+                clientRouterRule =  clientRouteRequest
                     clientIdx
                     selectedClientReqQueue
                     requestArbiterByServer

bs/ClkDivider.bs

@@ -34,7 +34,7 @@ mkClkDivider fileHandle = do
           counter := if (counter == hi_value)
                     then 0
                     else counter + 1
-    
+
     return $
       interface ClkDivider
         reset :: Action

bs/Deserializer.bs

@@ -1,15 +1,15 @@
 package Deserializer(
   mkDeserialize,
   IDeserializer(..),
-  State(..)) 
+  State(..))
   where
 
 import ClkDivider
 import State
 
 
-interface (IDeserializer :: # -> # -> *) clkFreq baudRate = 
+interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
-  get         ::  Bit 8            
+  get         ::  Bit 8
   putBitIn    :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
 
 mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
@@ -35,10 +35,10 @@ mkDeserialize fileHandle = do
           ftdiState := ftdiState' ftdiState
 
       {-# ASSERT fire when enabled #-}
-        "SAMPLING" : when 
+        "SAMPLING" : when
           DATA(n) <- ftdiState,
           n >= 0,
-          n <= 7, 
+          n <= 7,
           let sampleTrigger = clkDivider.isHalfCycle
             in sampleTrigger
           ==>
@@ -48,6 +48,6 @@ mkDeserialize fileHandle = do
   return $
     interface IDeserializer
     {get      = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
-    ;putBitIn bit = 
+    ;putBitIn bit =
       ftdiRxIn := bit
     }

bs/Serializer.bs

@@ -1,7 +1,7 @@
 package Serializer(
   mkSerialize,
   ISerializer(..),
-  State(..)) 
+  State(..))
   where
 
 import ClkDivider
@@ -14,7 +14,7 @@ serialize ftdiState dataReg =
         (DATA n) -> dataReg[n:n]
         _        -> 1'b1
 
-interface (ISerializer :: # -> # -> *) clkFreq baudRate = 
+interface (ISerializer :: # -> # -> *) clkFreq baudRate =
   putBit8    :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
   bitLineOut ::  Bit 1            {-# always_ready #-}
 
@@ -29,8 +29,8 @@ mkSerialize fileHandle = do
   addRules $
     rules
       {-# ASSERT fire when enabled #-}
-      "ADVANCE UART STATE WHEN NOT IDLE" : when 
+      "ADVANCE UART STATE WHEN NOT IDLE" : when
-        (ftdiState /= IDLE), 
+        (ftdiState /= IDLE),
         (clkDivider.isAdvancing) ==>
         do
           ftdiState := ftdiState' ftdiState
@@ -42,11 +42,10 @@ mkSerialize fileHandle = do
 
   return $
     interface ISerializer
-      putBit8  bit8Val = 
+      putBit8  bit8Val =
         do
           clkDivider.reset
-          dataReg := bit8Val 
+          dataReg := bit8Val
           ftdiState := ftdiState' ftdiState
         when (ftdiState == IDLE)
       bitLineOut = ftdiTxOut
-    

bs/State.bs

@@ -2,15 +2,15 @@ package State(
   State(..),
   ftdiState') where
 
-data State = IDLE 
+data State = IDLE
-           | START 
+           | START
-           | DATA (UInt (TLog 8)) 
+           | DATA (UInt (TLog 8))
-           | PARITY 
+           | PARITY
            | STOP
            deriving (Bits, Eq, FShow)
 
 ftdiState' :: State -> State
-ftdiState' state = 
+ftdiState' state =
   case state of
     IDLE    -> START
     START   -> DATA(0)