Artturin/RiscV-Formal
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RiscV-Formal/hs
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Yehowshua Immanuel 2b1c486c17 created Decode result
2025-03-05 09:04:54 -05:00
..
Peripherals clean up warnings a bit 2025-03-04 23:54:30 -05:00
Bus.hs clean up warnings a bit 2025-03-04 23:54:30 -05:00
BusTypes.hs initial support for exceptions 2025-03-02 23:12:02 -05:00
Cpu.hs clean up warnings a bit 2025-03-04 23:54:30 -05:00
Decode.hs created Decode result 2025-03-05 09:04:54 -05:00
DecodeTypes.hs created Decode result 2025-03-05 09:04:54 -05:00
Exceptions.hs created Decode result 2025-03-05 09:04:54 -05:00
Fetch.hs created Decode result 2025-03-05 09:04:54 -05:00
RegFiles.hs initial support for exceptions 2025-03-02 23:12:02 -05:00
Simulation.hs created Decode result 2025-03-05 09:04:54 -05:00
Types.hs hopefully progressing to a more scalable bus architecture 2025-02-25 14:24:54 -05:00