forked from Yehowshua/RiscV-Formal
52 lines
1.4 KiB
Haskell
52 lines
1.4 KiB
Haskell
{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Fetch(
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fetchInstruction,
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debugInsn,
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FetchResult(..),
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) where
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import Clash.Prelude
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import qualified Prelude as P
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import Types(Addr, Insn)
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import Bus(read)
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import Bus(Peripherals(..))
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import BusTypes(
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ReadRequest(..),
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TransactionSize(..),
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BusVal(..),
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BusError(..))
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import Exceptions(Exception(..))
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import Util((|>))
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data FetchResult = Instruction Insn
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| InstructionException Exception
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deriving (Generic, Show, Eq, NFDataX)
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fetchInstruction :: Peripherals -> Addr -> IO FetchResult
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fetchInstruction peripherals addr =
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do
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readReasponse <-Bus.read (BusTypes.Request addr BusTypes.SizeFullWord) peripherals
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case readReasponse of
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Right (BusFullWord insn) ->
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pure |> Instruction insn
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Left UnAligned ->
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pure |> InstructionException (InstructionAddressMisaligned addr)
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Left UnMapped ->
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pure |> InstructionException (InstructionAccessFault addr)
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Right _ ->
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pure |> InstructionException (InstructionAccessFault addr)
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debugInsn :: FetchResult -> String
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debugInsn fetchResult =
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case fetchResult of
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Instruction insn ->
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"Instruction raw binary | "
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P.++ binaryInsn
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P.++ " (" P.++ show insn P.++ ")"
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where
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binaryInsn = show (bitCoerce insn :: BitVector 32)
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InstructionException e -> show e
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