Artturin/RiscV-Formal
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11 commits

Author SHA1 Message Date
Yehowshua Immanuel 69f5cdee6a added needed context and getting ready to implement execute 2025-03-10 22:26:38 -04:00
Yehowshua Immanuel 63a73d3f71 now fetching from ram correctly as ram is 32 bit word not byte indexed 2025-03-07 21:41:46 -05:00
Yehowshua Immanuel 0792bf3c7d Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
Yehowshua Immanuel 67b44dedc0 clean up warnings a bit 2025-03-04 23:54:30 -05:00
Yehowshua Immanuel 88ec010f98 initial support for exceptions 2025-03-02 23:12:02 -05:00
Yehowshua Immanuel 5552ad3d4a bus architecture re-built I think 2025-02-26 13:05:02 -05:00
Yehowshua Immanuel c8b192cade prep for notable re-org 2025-02-26 02:24:23 -05:00
Yehowshua Immanuel 024115e389 Uart now has correct write implementation presumably 2025-02-26 01:51:33 -05:00
Yehowshua Immanuel 8d5cd862ab more progress on UART read 2025-02-25 23:47:00 -05:00
Yehowshua Immanuel 7265728932 read getting closer to being done 2025-02-25 19:09:37 -05:00
Yehowshua Immanuel 1f9bd2f015 hopefully progressing to a more scalable bus architecture 2025-02-25 14:24:54 -05:00