diff --git a/hs/Cpu.hs b/hs/Cpu.hs
index b18ee61..8dae856 100644
--- a/hs/Cpu.hs
+++ b/hs/Cpu.hs
@@ -32,7 +32,7 @@ data RISCVCPU = RISCVCPU
 riscvCPUInit :: RISCVCPU
 riscvCPUInit =
   RISCVCPU
-    { pc = 0 -- 0x8000_0000
+    { pc = 0x8000_0000
     , gpr = gprInit
     , fpr = fprInit
     , csr = csrInit
diff --git a/hs/Fetch.hs b/hs/Fetch.hs
index 8f444de..120c13a 100644
--- a/hs/Fetch.hs
+++ b/hs/Fetch.hs
@@ -3,7 +3,9 @@
 
 module Fetch(
   fetchInstruction,
-  FetchResult(..)) where
+  fetchInstruction1,
+  FetchResult(..),
+  FetchResult1(..)) where
 
 import Clash.Prelude
 import Types(Mem, Addr, Insn)
diff --git a/hs/Simulation.hs b/hs/Simulation.hs
index 66a9f5e..13cbf43 100644
--- a/hs/Simulation.hs
+++ b/hs/Simulation.hs
@@ -19,11 +19,12 @@ import Bus(Peripherals(..))
 import Cpu(
   RISCVCPU(..),
   riscvCPUInit)
-import Fetch(fetchInstruction, FetchResult (Instruction, Misaligned))
+import Fetch(fetchInstruction, FetchResult (Instruction, Misaligned), fetchInstruction1, FetchResult1(..))
 import Isa.Decode(decode)
 
 import Debug.Trace
 import Types (Insn)
+import Control.Monad.RWS (MonadState(put))
 
 data Args = Args {
     firmware :: FilePath
@@ -39,9 +40,6 @@ data Machine = Machine
   }
   deriving (Generic, Show, Eq, NFDataX)
 
--- machine :: Machine
--- machine = machineInit
-
 machine' :: Machine -> Machine
 machine' machine =
   let
@@ -63,12 +61,33 @@ machine' machine =
           opcode = decode insn
       Misaligned addr -> undefined
 
+debugInsn :: FetchResult1 -> String
+debugInsn fetchResult = 
+  case fetchResult of
+    Instruction1 insn ->
+      "Decoded instruction: " P.++ show opcode
+                      P.++ " | Binary: " P.++ binaryInsn
+                      P.++ " (" P.++ show insn P.++ ")"
+      where
+        binaryInsn = show (bitCoerce insn :: BitVector 32)
+        opcode = decode insn
+    InstructionException e -> show e
+
 simulationLoop :: Int -> Machine -> IO [Machine]
-simulationLoop 0 state = return [state]
-simulationLoop n state = do
-  let newState = machine' state
-  rest <- simulationLoop (n - 1) newState
-  return (state : rest)
+simulationLoop 0 machine = return [machine]
+simulationLoop n machine = do
+  -- let newState = machine' machine
+  let machinePeripherals = peripherals machine
+      currPc = pc $ cpu machine
+  fetchResult <- fetchInstruction1 machinePeripherals currPc
+  putStrLn $ debugInsn fetchResult
+  let pc' = currPc + 4
+      cpu' = (cpu machine) { pc = pc' }
+      machine' = machine { cpu = cpu' }
+  -- let machine' = machine { cpu = cpu $ machine { pc = pc $ cpu machine + 4 } }
+  rest <- simulationLoop (n - 1) machine'
+  return (machine : rest)
+
 
 simulation :: Args -> IO Simulation
 simulation args = do