diff --git a/hs/Bus.hs b/hs/Bus.hs
index bda78a6..5c11dda 100644
--- a/hs/Bus.hs
+++ b/hs/Bus.hs
@@ -18,10 +18,8 @@ import BusTypes(
     ReadRequest(..),
     BusVal(..),
   )
-import Types(Addr,
-             Byte, HalfWord, FullWord, DoubleWord, QuadWord)
-import Peripherals.Ram(read, write, bytesInRam)
-import Distribution.Types.UnitId (DefUnitId(unDefUnitId))
+import Types(Addr)
+import Peripherals.Ram(write, bytesInRam)
 
 data Peripherals = Peripherals
   {
@@ -40,7 +38,7 @@ busValToTransactionSize (BusDoubleWord _) = SizeDoubleWord
 busValToTransactionSize (BusQuadWord _)   = SizeQuadWord
 
 alignCheck :: Addr -> TransactionSize -> Bool
-alignCheck addr SizeByte       = True
+alignCheck _    SizeByte       = True
 alignCheck addr SizeHalfWord   = addr `mod` 2 == 0
 alignCheck addr SizeFullWord   = addr `mod` 4 == 0
 alignCheck addr SizeDoubleWord = addr `mod` 8 == 0
diff --git a/hs/Cpu.hs b/hs/Cpu.hs
index 8dae856..f1fe22b 100644
--- a/hs/Cpu.hs
+++ b/hs/Cpu.hs
@@ -7,9 +7,8 @@ module Cpu(
   riscvCPUInit) where
 
 import Clash.Prelude
-import Types(Pc, Mem)
+import Types(Pc)
 import RegFiles(GPR, FPR, CSR, gprInit, fprInit, csrInit)
-import Peripherals.Ram(Ram)
 
 data Endian = Big | Little
   deriving (Generic, Show, Eq, NFDataX)
diff --git a/hs/Exceptions.hs b/hs/Exceptions.hs
index c5fe617..24639a0 100644
--- a/hs/Exceptions.hs
+++ b/hs/Exceptions.hs
@@ -30,7 +30,6 @@ data Exception =
     | EnvironmentCallFromMMode
     | InstructionPageFault
     | LoadPageFault
-    | Reserved
     | StoreAMOPageFault
     | DoubleTrap
     | SoftwareCheck
@@ -84,7 +83,6 @@ isSynchronousException EnvironmentCallFromSMode     = True
 isSynchronousException EnvironmentCallFromMMode     = True
 isSynchronousException InstructionPageFault         = True
 isSynchronousException LoadPageFault                = True
-isSynchronousException Reserved                     = True
 isSynchronousException StoreAMOPageFault            = True
 isSynchronousException DoubleTrap                   = True
 isSynchronousException SoftwareCheck                = True
diff --git a/hs/Fetch.hs b/hs/Fetch.hs
index e0dfe28..c98818a 100644
--- a/hs/Fetch.hs
+++ b/hs/Fetch.hs
@@ -7,18 +7,15 @@ module Fetch(
   ) where
 
 import Clash.Prelude
-import Types(Mem, Addr, Insn)
-import Bus(ReadResponse, WriteResponse, read)
+import Types(Addr, Insn)
+import Bus(read)
 import Bus(Peripherals(..))
 import BusTypes(
   ReadRequest(..),
   TransactionSize(..),
   BusVal(..),
   BusError(..))
-import Exceptions(Exception(..), exceptionCode, isSynchronousException)
-
-import GHC.IO (IO)
-import GHC.Base (Applicative(pure))
+import Exceptions(Exception(..))
 
 data FetchResult  = Instruction Insn
                    | InstructionException Exception
diff --git a/hs/Peripherals/Ram.hs b/hs/Peripherals/Ram.hs
index df3b949..f3e8d0a 100644
--- a/hs/Peripherals/Ram.hs
+++ b/hs/Peripherals/Ram.hs
@@ -13,14 +13,13 @@ module Peripherals.Ram(
   write,
   ) where
 
-import Clash.Prelude hiding (read)
+import Clash.Prelude hiding (empty, read)
 import qualified Prelude as P
 import qualified Data.ByteString.Lazy as BL
 import Data.Binary.Get
 import Data.Int (Int32)
 import qualified Clash.Sized.Vector as Vec
-import Types(Addr,
-             Byte, HalfWord, FullWord, DoubleWord, QuadWord)
+import Types(Addr, FullWord, DoubleWord)
 import BusTypes(
     TransactionSize(..),
     BusVal(..),
diff --git a/hs/Peripherals/Uart.hs b/hs/Peripherals/Uart.hs
index 9fa718b..7d80fd0 100644
--- a/hs/Peripherals/Uart.hs
+++ b/hs/Peripherals/Uart.hs
@@ -5,20 +5,15 @@ import Types (Byte)
 import Data.Char (ord, chr)
 
 import Peripherals.UartCFFI (
-    initTerminal,
-    restoreTerminal,
     getCharFromTerminal,
     writeCharToTerminal,
     isCharAvailable,
-    setupSigintHandler,
-    wasCtrlCReceived
   )
 
 import BusTypes (
     TransactionSize(..),
     BusVal(..),
   )
-import GHC.Generics (URec(UAddr), Generic (from))
 
 -- based on a 16550 UART which has an address space of 8 bytes
 type UartAddr = Unsigned 3
diff --git a/hs/Peripherals/UartCFFI.hs b/hs/Peripherals/UartCFFI.hs
index b0998e9..76a4186 100644
--- a/hs/Peripherals/UartCFFI.hs
+++ b/hs/Peripherals/UartCFFI.hs
@@ -7,13 +7,11 @@ module Peripherals.UartCFFI (
     writeCharToTerminal,
     isCharAvailable,
     setupSigintHandler,
-    wasCtrlCReceived
+    ctrlCReceived
 ) where
 
 import Prelude
 import Foreign.C.Types
-import Foreign.C.String
-import Foreign.Ptr
 import Data.Char (chr, ord)
 
 -- Foreign imports directly corresponding to the C functions
diff --git a/hs/Simulation.hs b/hs/Simulation.hs
index e752d04..e1384b6 100644
--- a/hs/Simulation.hs
+++ b/hs/Simulation.hs
@@ -22,10 +22,6 @@ import Cpu(
 import Fetch(fetchInstruction, FetchResult (..))
 import Isa.Decode(decode)
 
-import Debug.Trace
-import Types (Insn)
-import Control.Monad.RWS (MonadState(put))
-
 data Args = Args {
     firmware :: FilePath
     } deriving (Show)
@@ -71,12 +67,12 @@ simulation args = do
   initializedPeripherals <- setupPeripherals (firmware args)
   case initializedPeripherals of
     InitializationError e -> return $ Failure e
-    InitializedPeripherals ram -> do
+    InitializedPeripherals ramDevice -> do
 
       let initState =
             Machine {
               cpu = riscvCPUInit,
-              peripherals = Bus.Peripherals ram
+              peripherals = Bus.Peripherals ramDevice
               }
       sim <- simulationLoop 15 initState
       teardownPeripherals