From 4729d79b23ba8d82443ad70fd63044c84a3967c3 Mon Sep 17 00:00:00 2001
From: Yehowshua Immanuel <yehowshua@joyofhardware.com>
Date: Tue, 4 Mar 2025 23:05:52 -0500
Subject: [PATCH] refactoring towards types that can handle exceptions between
 stages

---
 hs/Cpu.hs        | 11 ++++++-----
 hs/Simulation.hs |  6 ++----
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/hs/Cpu.hs b/hs/Cpu.hs
index 2046d18..b18ee61 100644
--- a/hs/Cpu.hs
+++ b/hs/Cpu.hs
@@ -32,8 +32,9 @@ data RISCVCPU = RISCVCPU
 riscvCPUInit :: RISCVCPU
 riscvCPUInit =
   RISCVCPU
-    0
-    gprInit
-    fprInit
-    csrInit
-    MachineMode
+    { pc = 0 -- 0x8000_0000
+    , gpr = gprInit
+    , fpr = fprInit
+    , csr = csrInit
+    , privilegeLevel = MachineMode
+    }
diff --git a/hs/Simulation.hs b/hs/Simulation.hs
index 289d4e6..66a9f5e 100644
--- a/hs/Simulation.hs
+++ b/hs/Simulation.hs
@@ -23,6 +23,7 @@ import Fetch(fetchInstruction, FetchResult (Instruction, Misaligned))
 import Isa.Decode(decode)
 
 import Debug.Trace
+import Types (Insn)
 
 data Args = Args {
     firmware :: FilePath
@@ -48,9 +49,6 @@ machine' machine =
     machineMem  = ram $ machinePeripherals
     machineCPU  = cpu machine
     machinePC   = pc machineCPU
-    addr = 0 :: Integer
-    mem' = replace addr (3) machineMem
-    peripherals' = machinePeripherals { ram = mem' }
     cpu' = machineCPU { pc = machinePC + 4 }
 
   in
@@ -60,7 +58,7 @@ machine' machine =
         in trace ("Decoded instruction: " P.++ show opcode
                   P.++ " | Binary: " P.++ binaryInsn
                   P.++ " (" P.++ show insn P.++ ")") $
-           machine { cpu = cpu', peripherals = peripherals' }
+           machine { cpu = cpu' }
         where
           opcode = decode insn
       Misaligned addr -> undefined