forked from Yehowshua/RiscV-Formal
Uart now has correct write implementation presumably
This commit is contained in:
parent
8d5cd862ab
commit
024115e389
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@ -8,6 +8,8 @@
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static volatile bool ctrl_c_received = false;
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static volatile bool ctrl_c_received = false;
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static char last_char = '\0';
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static char last_char = '\0';
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int is_char_available();
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void sigint_handler(int sig_num) {
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void sigint_handler(int sig_num) {
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ctrl_c_received = true;
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ctrl_c_received = true;
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}
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}
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22
hello.asm
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hello.asm
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@ -1,22 +0,0 @@
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./rv_tests/hello_world/hello.bin: file format binary
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Disassembly of section .data:
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0000000000000000 <.data>:
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0: 00000597 auipc a1,0x0
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4: 02458593 add a1,a1,36 # 0x24
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8: 0005c503 lbu a0,0(a1)
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c: 00050a63 beqz a0,0x20
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10: 100002b7 lui t0,0x10000
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14: 00a28023 sb a0,0(t0) # 0x10000000
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18: 00158593 add a1,a1,1
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1c: fedff06f j 0x8
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20: 0000006f j 0x20
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24: 6548 ld a0,136(a0)
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26: 6c6c ld a1,216(s0)
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28: 77202c6f jal s8,0x279a
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2c: 646c726f jal tp,0xc7672
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30: 0a21 add s4,s4,8
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...
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14
hs/Bus.hs
14
hs/Bus.hs
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@ -4,6 +4,7 @@ module Bus() where
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import Clash.Prelude
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import Clash.Prelude
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import Peripherals.Ram(Ram, RamLine, read, RamAddr)
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import Peripherals.Ram(Ram, RamLine, read, RamAddr)
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import Peripherals.Uart(UartAddr, read)
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import Machine(Peripherals(..))
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import Machine(Peripherals(..))
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import BusTypes(
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import BusTypes(
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BusError(..),
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BusError(..),
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@ -35,10 +36,19 @@ alignCheck addr SizeQuadWord = addr `mod` 16 == 0
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read :: Request -> Peripherals -> IO ReadResponse
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read :: Request -> Peripherals -> IO ReadResponse
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read (Request addr size) peripherals
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read (Request addr size) peripherals
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| not (alignCheck addr size) = return $ ReadResponse $ Error UnAligned
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| not (alignCheck addr size) = return $ ReadResponse $ Error UnAligned
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| (addr > ramStart) && (addr < ramEnd) =
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| (addr >= ramStart) && (addr <= ramEnd) =
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return $ ReadResponse $ Result $ Peripherals.Ram.read size ramAddr (ram peripherals)
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return $
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ReadResponse $
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Result $ Peripherals.Ram.read size ramAddr (ram peripherals)
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| (addr >= uartStart) && (addr <= uartEnd) =
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ReadResponse . Result <$>
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Peripherals.Uart.read size uartAddr
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| otherwise = return $ ReadResponse $ Error UnMapped
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| otherwise = return $ ReadResponse $ Error UnMapped
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where
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where
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ramAddrNoOffset = addr - ramStart
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ramAddrNoOffset = addr - ramStart
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ramAddr :: RamAddr
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ramAddr :: RamAddr
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ramAddr = resize ramAddrNoOffset
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ramAddr = resize ramAddrNoOffset
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uartAddrNoOffset = addr - uartStart
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uartAddr :: UartAddr
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uartAddr = resize uartAddrNoOffset
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@ -1,8 +1,8 @@
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module Peripherals.Uart (read) where
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module Peripherals.Uart (read, write, UartAddr) where
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import Clash.Prelude hiding (read)
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import Clash.Prelude hiding (read)
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import Types (Byte)
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import Types (Byte)
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import Data.Char (ord)
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import Data.Char (ord, chr)
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import Peripherals.UartCFFI (
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import Peripherals.UartCFFI (
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initTerminal,
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initTerminal,
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@ -20,6 +20,7 @@ import BusTypes (
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ReadResponse(..),
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ReadResponse(..),
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WriteResponse(..)
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WriteResponse(..)
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)
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)
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import GHC.Generics (URec(UAddr), Generic (from))
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-- based on a 16550 UART which has an address space of 8 bytes
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-- based on a 16550 UART which has an address space of 8 bytes
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type UartAddr = Unsigned 3
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type UartAddr = Unsigned 3
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@ -28,6 +29,9 @@ type UartAddr = Unsigned 3
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rbrAddr :: UartAddr
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rbrAddr :: UartAddr
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rbrAddr = 0x0
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rbrAddr = 0x0
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thrAddr :: UartAddr
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thrAddr = 0x0
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-- Line Status Register address
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-- Line Status Register address
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lsrAddr :: UartAddr
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lsrAddr :: UartAddr
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lsrAddr = 0x5
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lsrAddr = 0x5
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@ -50,8 +54,11 @@ buildRBR = do
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-- Reads the Line Status Register (LSR) to check character availability
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-- Reads the Line Status Register (LSR) to check character availability
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buildLSR :: IO Byte
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buildLSR :: IO Byte
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buildLSR = do
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buildLSR = do
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char_available <- isCharAvailable
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(char_available :: Byte) <- fromIntegral <$> isCharAvailable
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return $ fromIntegral char_available
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-- highly unlikely that we overflow stdout buffer, so we set
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-- transmit to always ready
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let (transmit_ready :: Byte) = 0b0010_0000
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return (char_available .|. transmit_ready)
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-- Updated 'read' function to handle RBR and LSR reads
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-- Updated 'read' function to handle RBR and LSR reads
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read :: TransactionSize -> UartAddr -> IO BusVal
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read :: TransactionSize -> UartAddr -> IO BusVal
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@ -59,3 +66,18 @@ read size addr
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| addr == rbrAddr = busValFromByte size <$> buildRBR
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| addr == rbrAddr = busValFromByte size <$> buildRBR
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| addr == lsrAddr = busValFromByte size <$> buildLSR
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| addr == lsrAddr = busValFromByte size <$> buildLSR
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| otherwise = return $ busValFromByte size 0x00
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| otherwise = return $ busValFromByte size 0x00
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extractLowestByte :: BusVal -> Byte
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extractLowestByte (BusByte b) = b
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extractLowestByte (BusHalfWord hw) = resize hw
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extractLowestByte (BusFullWord fw) = resize fw
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extractLowestByte (BusDoubleWord dw) = resize dw
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extractLowestByte (BusQuadWord qw) = resize qw
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byteToChar :: Byte -> Char
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byteToChar = chr . fromIntegral
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write :: BusVal -> UartAddr -> IO ()
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write val addr
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| addr == thrAddr = writeCharToTerminal $ byteToChar $ extractLowestByte val
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| otherwise = return ()
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@ -34,7 +34,7 @@ $(BIN): $(ELF)
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# Run in QEMU
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# Run in QEMU
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run: $(BIN)
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run: $(BIN)
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echo "Press CTRL+A then X to exit QEMU"
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echo "Press CTRL+A then X to exit QEMU"
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$(QEMU) -machine virt -nographic -bios none -kernel $(BIN) -device loader,file=$(BIN),addr=0x80000000 -device sifive_uart
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$(QEMU) -machine virt -nographic -bios none -kernel $(BIN) -device loader,file=$(BIN),addr=0x80000000
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# Clean up generated files
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# Clean up generated files
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clean:
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clean:
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